View BBT3821-JH_5790454.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 ? fn7483.2 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-352-6832 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005. all rights reserved all other trademarks mentioned are the property of their respective owners. bbt3821 octal 2.488gbps to 3.187gbps/ lane retimer features ? 8 lanes of clock & data recovery and retiming; 4 in each direction ? differential input/output ? wide operating data rate range: 2.488gbps to 3.1875gbps, and 1.244gbps to 1.59325gbps ? ultra low-power operation (195mw typical per lane, 1550mw typical total consumption) ? low power version available for lx4 applications ? 17mm square low profile 192 pin 1.0mm pitch ebga package ? compliant to the ieee 802.3 10gbase-lx4(wwdm), 10gbase-cx4, and xaui specifications ? reset jitter domain ? meets 802.3ae and 802.3ak jitter requirements with significant margin ? received data aligned to local reference clock for retransmission ? increase driving distance ? lx4: up to 40 inches of fr-4 traces or 500 meters of mmf fiber at 3.1875gbps ? cx4: over 15 meters of compatible cable ? deskewing and lane-to-lane alignment ? 0.13mm pure-digital cmos technology ? 1.5v core supply, control i/o 2.5v tolerant ? clock compensation ? tx/rx rate matching via idle insertion/deletion up to 100ppm clock difference ? receive signal detect and 16 levels of receiver equalization for media compensation ? cml cx4 transmission output with 16 settable levels of pre-emphasis, eight on xaui side ? single-ended or differential input lower-speed reference clock ? ease of testing ? complete suite of ingress-egress loopbacks ? full 802.3ae pattern generation and test, including cjpat & crpat ? prbs (both 2 23 -1 and 13458 byte) built-in self tests, error flags and count output ? jtag and ac-jtag boundary scan ? long run length (512 bit) frequency lock ideal for proprietary encoding schemes ? extensive configuration and status reporting via 802.3 clause 45 compliant mdc/mdio serial interface ? automatic load of bbt3821 control and all xenpak registers from eeprom or dom circuit figure 1. functional block diagram egress 2 egress 0 ingress 2 ingress 0 clock multiplier rfcp rfcn rx0n rx0p 3.125g receive parallel data mdio/mdc register file tx0n tx0p deserializer and comma detector 8b/10b decoder 8b/10b encoder & mux clock & data recovery receive fifo i 2 c interface mdc mdio sda scl ingress 3 egress 3 ingress 1 egress 1 data sheet july 20, 2005
2 table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 list of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 receiver operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 loss of signal detection, termination & equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 clock and data recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 byte alignment (code-group alignment) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 8b/10b decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 receive fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 deskew (lane to lane) alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 clock compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 transmitter operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 8b/10b encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 pre-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 8b/10b coding and decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8 bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 10 bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 error indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 loss of signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 byte or lane synchronization failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 channel fault indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 coding violation, disparity & fifo errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 loopback modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 pma loopback (1.0.0 & 1.c004.[11:8]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 phy xs (serial) loopback (4.0.14 & 4.c004.[11:8]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 pcs parallel network loopback (3.c004.[3:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 pcs (parallel) loopback (4.c004.[3:0] & optionally 3.0.14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 serial test loopbacks (1.c004.12 & 4.c004.12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 serial management interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 mdio register addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 i2c space interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 nvr registers & eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 auto-configuring control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 dom registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 general purpose (gpio) pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 lasi registers & i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 reading additional eeprom space via the i2c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 writing eeprom space through the i2c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 bbt3821
3 block writes to eeprom space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 byte writes to eeprom space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 mdio registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 pma/pmd device 1 mdio registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 ieee pma/pmd registers (1.0 to 1.15/1.000f? h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 xenpak-defined registers (1.8000?h to 1.8106?h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 xenpak lasi and dom registers (1.9000?h to 1.9007?h & 1.a000?h to 1.a100?h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 vendor-specific pma/pmd and gpio registers (1.c001?h to 1.c01d?h ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 pcs device 3 mdio registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 ieee pcs registers (3.0 to 3.25/3.0019?h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 vendor-specific pcs registers (3.c000?h to 3.c00e?h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 phy xs device 4 mdio registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 ieee phy xs registers (4.0 to 4.25/4.0019?h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 vendor-specific phy xs registers (4.c000?h to 4.c00b?h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 auto-configure register list. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 jtag & ac-jtag operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 bist operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 pin specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 pin diagram 17x17mm (16*16 ball matrix) 192-pin ebga-b package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 ac and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 cx4/lx4/xaui re-timer setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 recommended analog power and ground plane splits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 recommended power supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 xenpak/xpak/x2 interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 cx4 interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 lx4 interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 mdio/mdc interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 i2c interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 dom interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 lasi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 intersil corporation contact information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 bbt3821
4 list of figures figure 1. functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2. detailed functional block diagram (bist omitted) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. pre-emphasis output illustration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 4. ieee and vendor specific fault and status registers (equivalent schematic). . . . . . . . . . . . . . 14 figure 5. lasi equivalent schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 6. block diagram of bist operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 7. top view of pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 8. ebga-192 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 9. differential output signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 10. lane to lane differential skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 11. eye diagram definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 12. byte synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 13. lane-lane alignment operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 14. retransmit latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 15. mdio frame and register timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 16. mdio interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 17. mdio timing after soft reset (d.0.15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 18. beginning i2c nv r read at the end of reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 19. i2c bus interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 20. nvr/dom sequential read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 21. nvr sequential write one page operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 22. i2c single byte read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 23. single byte write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 24. i2c operation timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 25. vddpr clamp circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 26. resistive divider circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 bbt3821
5 list of tables table 1. valid 10b/8b decoder & encoder patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 2. devad device address table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3. mdio management frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 4. mdio pma/pmd devad 1 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 5. ieee pma/pmd control 1 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 6. ieee pma/pmd status 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 7. ieee pma/pmd, pcs, phy xs, speed ability register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 8. ieee devices in package registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 9. ieee pma/pmd type select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 10. ieee pma/pmd status 2 device present & fault summary register . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 11. ieee transmit disable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 12. ieee pmd signal detect register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 13. ieee extended pma/pmd capability register(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 14. ieee package identifier registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 15. xenpak nvr control & status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 16. i2c one-byte operation device address register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 17. i2c one-byte operation memory address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 18. i2c one-byte operation read data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 19. i2c one-byte operation write data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 20. nvr i2c operation control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 21. nvr i2c operation status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 22. xenpak nvr register copy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 23. xenpak digital optical monitoring (dom) capability register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 24. xenpak lasi rx_alarm control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 25. xenpak lasi tx_alarm control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 26. xenpak lasi control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 27. xenpak lasi rx_alarm status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 28. xenpak lasi tx_alarm status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 29. xenpak lasi status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 30. xenpak dom tx_flag control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 31. xenpak dom rx_flag control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 32. xenpak dom alarm & warning thresh old registers copy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 33. xenpak dom monitored a/d values register copy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 34. xenpak optional dom status bits register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 35. xenpak dom extended capability register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 36. xenpak dom alarm flags register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 37. xenpak dom warning flags register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 38. xenpak dom operation control and status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 39. pma control 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 40. pma serial loop back control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 41. pma pre-emphasis control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 42. pma pre-emphasis control settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 43. pma/pmd equalization control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 44. pma sig_det and los detector status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 45. pma/pmd miscellaneous adjustment register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 46. pma/pmd/pcs/phy xs soft reset register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 bbt3821
6 table 47. gpio pin direction configure register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 48. gpio pin input status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 49. tx_fault & gpio pin to lasi configure register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 50. gpio pin output register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 51. dom control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 52. dom periodic update waiting time values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 53. dom indirect mode start address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 54. dom indirect mode device address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 55. optical status & control pin polarity register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 56. mdio pcs devad 3 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 57. ieee pcs control 1 regi ster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 58. ieee pcs status 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 59. ieee pcs type select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 60. ieee pcs status 2 device present & fault summary register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 61. ieee 10gbase-x pcs status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 62. ieee 10gbase-x pcs test control re gister . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 63. pcs control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 64. pcs control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 65. pcs or phy xs xaui_en control ove rride functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 66. pcs internal error code register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 67. pcs internal idle code register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 68. pcs parallel network loop back control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 69. pcs receive path test and status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 70. pma/pcs output control & test function register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 71. pcs/phy xs half rate clock control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 72. bist control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 73. bist error counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 74. mdio phy xs devad 4 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 75. ieee phy xs control 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 76. ieee phy xs status 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 77. ieee phy xs status 2 device present & fault summary register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 table 78. ieee 10gbase-x phy xgxs status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 79. ieee 10gbase-x phy xgxs test control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 80. phy xs control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 81. phy xs control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 82. phy xs internal error code register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 83. phy xs internal idle code register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 84. phy xs miscellaneous loop back control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 85. phy xs pre-emphasis control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 86. phy xs xaui pre-emphasis control settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 87. phy xs equalization control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 88. phy xs receive path test and status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 89. phy xs output and test function control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 90. phy xs status 4 los detector register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 91. phy xs control register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 92. auto-configure registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 93. jtag operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 94. clock pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 bbt3821
7 table 95. xaui (xenpak/xpak/x2) side serial data pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 96. pma/pmd (cx4/lx4) side serial data pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 97. jtag interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 98. management data interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 99. miscellaneous pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 100. i2c 2-wire serial data interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 101. voltage supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 102. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 103. recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 104. power dissipation and thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 105. pma serial pin i/o electrical spe cifications, cx4 mode (3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 106. pma serial pin i/o electrical spe cifications, lx4 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 107. phy xs serial pin i/o electrical specifications, xaui mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 108. external 1.2v cmos open drain i/o electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 109. 1.5v cmos input/output electr ical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 110. 2.5v tolerant open drain cm os input/output electrical specifications . . . . . . . . . . . . . . . . . . 62 table 111. other dc electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 112. reference clock requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 113. transmit serial differential outputs (see figure 9, figure 10 and figure 11). . . . . . . . . . . . . . . . . . . 63 table 114. receive serial differential in put timing requirements (see figure 11) . . . . . . . . . . . . . . . . . . . . . 63 table 115. mdio interface timing (from ieee 802.3ae) (see figure 15 to figure 17) . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 116. reset and mdio timing (see figure 17). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 117. reset and i2c serial interface timing (see figure 18 and figure 24). . . . . . . . . . . . . . . . . . . . . . . . . . . 64 bbt3821
8 figure 2. detailed functional block diagram (bist omitted) (see also figure 4 & figure 5 for mdio and l asi blocks and figure 6 for bist operation) ingress mdio register, lasi & common logic jtag tdi tdo tms tclk trstn 20x or 10x clock lx4_mode rstn xp_ena rfc p/n cdr deserializer & comma detector 10b/8b decoder rx fifo deskew cdr deserializer & comma detector 10b/8b decoder rx fifo deskew cdr equalizer signal detect deserializer & comma detector 10b/8b decoder rx fifo deskew cdr deserializer & comma detector 10b/8b decoder rx fifo deskew serialize r 8b/10b encoder, akr generator txfifo & error and orderset detector serialize r 8b/10b encoder, akr generator txfifo & error and orderset detector s e ria lize r 8b/10b encoder, akr generator txfifo & error and orderset detector s e ria lize r 8b/10b encoder, akr generator txfifo & error and orderset detector equalizer signal detect equalizer signal detect rxp0p/n cdr deserializer & comma detector 10b/8b decoder rx fifo deskew cdr d e se ria liz e r & comma detector 10b/8b decoder rx fifo deskew cdr deserializer & comma detector 10b/8b decoder rx fifo deskew cdr deserializer & comma detector 10b/8b decoder rx fifo deskew serializer 8b/10b encoder, akr generator txfifo & error and orderset detector serializer 8b/10b encoder, akr generator txfifo & error and orderset detector serializer 8b/10b encoder, akr generator txfifo & error and orderset detector serializer 8b/10b encoder, akr generator txfifo & error and orderset detector rxp1p/n rxp2p/n rxp3p/n equalizer signal detect txp0 p/n txp1 p/n txp2 p/n txp3 p/n equalizer, signal detect equalizer, signal detect equalizer, signal detect rcx0 p/n rcx1 p/n rcx2 p/n rcx3 p/n equalizer signal detect tcx0 p/n tcx1 p/n tcx2 p/n tcx3 p/n lx4/cx4 xaui txck20 bist pma loop back pcs // network loopback pcs // (phy xs) loopback phy xs (serial) loopback egress ingress egress bist_ena device address 3 pcs device address 4 phy xgxs device address 1 pma/pmd gpio[4:0] i 2 c wrtp sdc sda mdio engine mdc mdio padr[4:0] tx_ena[3:0] tx_fault lasi oprxxx(5 pins) optxxx(3 pins) tx_enc mf[3:0] bbt3821
9 general description the nliten bbt3821 is a fully in tegrated octal 2.488gbps to 3.1875gbps clock and data recovery (cdr) circuit and retimer ideal for high bandwidth serial electrical or optical communications systems. it extracts timing information and data from serial inputs at 2.488gbps to 3.1875gbps, covering 10 gigabit fiber channel (10gfc) and ieee 802.3 specified 10 gigabit ethernet extended attachment unit interface (xaui) rates. each bbt3821 accepts two sets of four high-speed differential serial signals, re-times them with a local reference clock, reduces jitter, and delivers eight clean high-speed signals. the bbt3821 provides a full-function xaui-to-10gbase-cx4 pma/pmd (compatible with the ieee 802.3ak specific ation), and also can be configured to provide the electrical port ion of a xaui-to-10gbase-lx4 pma/pmd, needing only laser dr ivers and photo detectors to be added. in both these applications, the xaui side can be configured to implement the xenpak msa_r3.0 specification, including full nvr and dom support. the xpak and x2 specifications currently all reference the xenpak specification, and are supported in exactly the same manner. the bbt3821 can also be used to enhance a single full-duplex 10 gigabit xaui link, extending the driving distance of the high-speed (2.488gbps to 3.1875gbps) differential traces to 40 inches of fr4 pcb (assuming a proper impedance-controlled layout). each lane can operate independently with a data transfer rate of within 100ppm of either 20x or 10x the local reference clock. the reference clock should be 156.25mhz for 10 gigabit ethernet xaui applications, and 159.375mhz for 10 gigabit fiber channel. other reference frequencies can be used for proprietary rates. for other applications, each of the 8 lanes can be operated independently, within the same data rate and clock restrictions. the nliten bbt3821 contains eight clock & data recovery units, 8b/10b decoders and encoders, and elastic buffers which provide the user with a simple interface for transferring data serially and recovering it on the receive side. when recovering an 8b/10b stream, a receive fifo aligns all incoming serial data to the local reference clock domain, adding or removing idle sequences as required. this simplifies implementation of an upstream asic by removing the requirement to deal with multiple clock domains. the retimer can also be configured to operate as eight non- encoded 10-bit retimers. allowing long strings of consecutive 1?s or 0?s (up to 512 bits), the nliten bbt3821 has the capacity to accommo date proprietary encoded data links at any data rate between 2.488gbps and 3.1875gbps (and for half rate operation from 1.244gbps to 1.59375gbps). the device configuration can be done through the use of the two line management data input/output (mdio) interface specified in ieee 802.3 claus e 45. the bbt3821 supports a 5-bit port address, and device addresses (devad) 1, 3 & 4. the initial values of the register s default to values controlled, where appropriate, by external configuration pins, and set to optimize the initial configuration for xaui, cx4, and xenpak/xpak/x2 use. op tionally, the bbt3821 configuration can be loaded at power-on or reset from the nvr eeprom or dom used for the xenpak/xpak/x2 registers. a full suite of loopback configurations is provided, including the (802.3ae required) xaui-transmit to xaui-receive loopback, and also the (802.3ae optional) phy xgxs loopback (effectively cx4/lx4-re ceive to cx4/lx4 transmit). lane-by-lane diagnostic loopback is available through vendor-specific mdio registers. the low-power version bbt3821lp-jh is selected for operation as an lx4 device at lowered supply voltages. functions the nliten bbt3821 serves three main functions: ? pre-emphasize the output and equalize the input in order to ?re-open? the data eye, thus allowing cx4 operation, and also increasing the available driving distance of the high-speed traces in xaui links. ? clock compensation by insertion and deletion of idle characters when 8b/10b encoding and decoding is enabled. ? automatic byte and lane alig nment, using both disparities of /k/ for byte alignment and either ||a|| or idle to data transitions for lane alignment. receiver operations loss of signal detection, termination & equalization each receiver lane detects and recovers the serial clock from the received data stream. an equalizer has been added to each receiver input buffer, which boosts high frequency edge response. the boost factor can be selected from 16 values (none to full) through the mdio registers, (see table 43 for the pma/pmd and table 87 for the phy xs). a nominally 100 ? on-chip transmission line terminating resistor is integrated with the in put equalizer. this eliminates the requirement of external te rmination resistors. it greatly improves the effectiveness of th e termination, providing the best signal integrity possible. there are also signal detect functions on each input lane, whose ?loss of signal? (los) and ?signal detect? (sig_det) outputs appear in the mdio vendor-specific registers at address 1.c00a?h (table 44) and 4.c00a?h (table 90). the los indication reflects the standard xaui specification, while the sig_det indication (cx4 inputs only) implements the cx4 function. these signals can also bbt3821
10 be routed to the mf[3:0] pins (see table 81 and table 99). the pma configuration determin es which of these signals will be reflected in the ieee pmd receive signal detect register at 1.10 (see tabl e 12), and contribute to the rx_fault bit in the ieee status register 2 at address 1.8 (see table 10) and the loca l_flt bit in the ieee pma/pmd status 1 register, at address 1.1, (see table 6). the phy xgxs los will be reflected in the ieee status registers at addresses 4.8 and 4.1 (see table 77 and table 76). the threshold of t he los detectors is controlled via the 'los_th' bits in the mdio registers at 1.c001'h, see table 39, for the pma/pmd, and for the phy xs at 4.c001'h, see table 81. clock and data recovery when the 8b/10b coding is used, the line rate receive clock is extracted from the transition rich 10-bit coded serial data stream independently on each lane. when 8b/10b coding is not used, longer run length (up to 512 1?s and 0?s) can be supported. the data rate of the received serial bit stream must be within 100ppm of the nominal bit rate (strictly within 200 ppm of the multiplied local reference clock) to guarantee proper reception. the receive clock locks to the input within 2s after a valid input data stream is applied. the received data is de-serialized and byte aligned. byte alignment (code-group alignment) unless the cdet bits of the mdio registers at address 3.c000?h (for pcs, see table 6 3) or 4.c000?h (for phy xs, see table 80) are turned off, the respective byte alignment units are activated. each byte alignment unit searches the coded incoming serial stream for a sequence defined in ieee 802.3-2002 clause 36 as a ?comma?. a comma is the sequence ?0011111? or ?1100000? depending on disparity, and is uniquely located in a valid 8b/10b coded data stream, appearing as the start of some control symbols, including the /k/ idle (k28.5). comma disparity action can be controlled via the same cdet bits of the registers [3:4].c000?h (see table 63 and table 80). any proprietary encoding scheme used should either incorporate these codes, or arrange byte alignment differently. upon detection of a comma, the byte alignment unit shifts the incoming data to align the received data properly in the 10-bit character field. two possible algorithms may be used for byte alignment. the default is that specified in the ieee802.3ae-2002 clause 48 s pecification, and is very robust. this algorithm relies on the 10b/8b decoder, and should not be used with pr oprietary encoding/decoding schemes. the alternative is to byte-align on any comma pattern. although quick to align, and normally quite reliable, this method is susceptible to realignment on certain single bit errors or on successive k28.7 characters, but could be preferable for proprietary coding schemes, or during debug. the algorithm selection is controlled via mdio register pcs_sync_en bits, for the pcs at address 3.c000?h (table 63), for the phy xs at address 4.c000?h (table 80), unless overridden by the respective xaui_en bits in the [3,4].c001?h registers (table 64 and table 81). up to a full code group may be deleted or modified while aligning the ?comma? code group correctly to the edges of the refclock. a comma received at any odd or even byte location, but at the proper byte boundary, will not cause any byte re- alignment. 8b/10b decoding the internal 10b decoding specified in the ieee802.3-2002 specification, section 36.2.4 in tables 36-1 & 36-2, and discussed in more detail in ?8b/10b coding and decoding? page 12, is enabled by default in the pcs and phy xs through the setting of the respective codecena bits to 1?b, and may be disabled through the mdio registers [3,4].c000?h (table 63 and table 80) by setting the respective bit to 0?b. note that the transmit encoding will also be disabled. although comma detection will still operate normally, the pcs_sync engine (see above) may not operate correctly on a proprietary coding scheme, unless byte sync is performed on k28.5 characters, and no code violations are to be expected in the proprietary data, and so should normally be disabled if the 8b/10b coding is turned off. the ?fallback? byte sync operations described above can still be used, if the encoding scheme meets the ?comma? rules; otherwise they should be disabled also via the cdet bits, and the user should expect unsynchronized 10-bit data to be forwarded to the transmitter. no clock compensation is then possible, and a synchronous reference clock should be used throughout. receive fifo the receive fifo performs two functions: 1. lane to lane alignment 2. clock compensation deskew (lane to lane) alignment trunking, also known as deske wing, means the alignment of packet data across multiple lanes. 8 bytes of rxfifo are dedicated for this lane to lane alignment in each direction. during high-speed transmission, different active and passive elements in the links may impart varying delays in the four lanes. in trunking mode, multiple lanes share the same clock (the local reference clock), which is used to transfer data for output on the serial transmitter. deskewing is accomplished by monitoring the contents of the fifos to detect either an /a/ code-group on every lane (an ||a|| ordered_set), or the boundary between idle sequences and any non-idle data (see table 1); the latter boundary defines the beginning of the packet. the choice of which alignment markers to use can be controlled by the a_align_dis bits in mdio [3,4].c000?h (see for pcs table 63 and for phy xs table 80), unless overridden by the respective xaui_en bits in the [3,4].c001?h registers (table 64 and table 81) to align on ||a||. when this alignment bbt3821
11 data is detected in all four lanes within the span of the alignment fifo, the deskewing (lane to lane) alignment operation is performed, and will be held until another ||a|| or idle-to- non-idle transition is detected again on the lanes. during this alignment, up to four code groups may be deleted on any lane. for correct operation, the xaui lane 0 signals should be connected to the bbt3821 lane 0 pins. the deskew algorithm state ma chines (each implemented according to ieee 802.3ae) are enabl ed by setting the dskw_sm_en bits (address [3,4].c000?h, see table 63 and/or table 80) to 1 or overriding them with the respective xaui_en bits in the [3,4].c001?h registers (table 64 and table 81). note that when one side?s dskw_sm_en is set to 1, the same side cal_en bit (address [3,4].c000?h, table 63/table 80) is ignored. when a dskw_sm_en bit is set to 0, lane deskew can still be enabled by setting cal_en, but the deskew action will be carried out without hysteresis. the user has the option to disable trunking, or to enable trunking across each set of 4 lanes, in the pcs (device 3) and phy xgxs (device 4), under control of the respective psync bits in registers [3,4].c000h. in trunking mode, the lanes may have phase differences, but they are expected to be frequency synchronous. in non-trunking mode, each received serial stream need only be within 100ppm of the nominal bit rate (2.488gbps to 3.1875gbps in full-speed mode or 1.244gbps to 1.59375g bps in half-speed mode). setting the psync bits high will enable the trunking mode, so that all transmitted data wil l be synchronized to the same clock. note that trunking mode is only possible if 8b/10b coding is activated, and all lanes have the same half-rate setting (see table 71). clock compensation in addition to deskew, the receive fifos also compensate for clock differences. since the received serial streams can, under worst case conditions, be off by up to 200ppm from the local clock domain, the received data must be adjusted to the local reference clock frequency. another 8 bytes of rxfifo are dedicated for clock compensation. the fifos achieve clock tolerance by identifying any of the idle patterns (/k/, /a/ or /r/ as defined by the ieee 802.3ae st andard) in the rece ived data and then adding or dropping idles as needed. the receive fifo does not store the actual idle sequences received but generates the number of idles needed to compensate for clock tolerance differences. the idle patterns retransmitted will be determined according to the ieee 802.3ae algorithm if the appropriate akr_sm_en bit is set in registers [3,4].c001?h (see table 64 and table 81). transmitter operations 8b/10b encoding the internal 10b encoding specified in the ieee802.3-2002 specification, section 36.2.4 in tables 36-1 & 36-2, and discussed in more detail in ?8b/10b coding and decoding? page 12, is enabled by default in the pcs and phy xs through the setting of the respective codecena bits to 1?b, and may be disabled through the mdio registers [3,4].c000?h (see table 63 and table 80) by setting the respective bit to 0?b. note that the receive decoding will also be disabled. the (decoded, synchronized and aligned) data is transferred via the transm it fifos, (normally) encoded, serialized and re-transmitted on the serial output pins, whose effective output impedance is nominally 100 ? differential. pre-emphasis in order to compensate for the loss of the high frequency signal component through pcb traces or the cx4 cable assembly, sixteen levels of programmable pre-emphasis have been provided on the cx4/lx4 pma serial transmit lanes, and eight levels on the xaui phy xs serial transmit lanes. the output signal is boosted immediately after any transition (see figure 3). this maximizes the data eye opening at the receiver inputs and enhances the bit error rate performance of the syst em. the mdio registers at addresses [1,4].c005?h (see table 41 and table 85) control the level of pre-emphasis for the pma/pmd (sixteen levels) and phy xgxs (eight levels) respectively, settable from none to the maximum. the initial default values of the pma/pmd register depend on th e lx4_mode configuration pin, and are set to the optimum values for cx4 or xaui (assumed best for lx4 drivers). both these registers may be auto-loaded (see auto-configuring control registers page 16) from an nvr eeprom on start-up or reset. v hi-pp v low-pp bit time bit time bit time 1 1 00 figure 3. pre-emphasis output illustration bbt3821
12 8b/10b coding and decoding 8 bit mode if 8b/10b encoding/decoding is turned on, the nliten bbt3821 expects to receive a properly encoded serial bit stream. the serial bit stream must be ordered ?abcdeifghj? with ?a? being the first bit received and ?j? the last. if the received data contains an error, the retimer will re-transmit it as an error or /e/ character. the character transmitted may be controlled via the error code registers [3,4].c002?h, table 66 and table 82. the internal decoding into, and encoding from, the fifos is listed in table 1 below. if the trans_en bit or xaui_en bit (mdio registers at addresses [3,4].c001?h, see table 64 and table 81 are set, all incoming xaui or cx4/lx4 idle patterns will be converted to the (internal) xgmii idle pattern set by the respective pcs or phy xs cont rol registers at addresses [3,4].c003?h, with a default value 107?h, the standard xgmii idle code (see table 67 and table 83) in the internal fifos. the first full column of idles after any column containing a non-idle will be stored in the respective elasticity fifo, and all subsequent full idle columns will repeat this pattern, until another column containing a non-idle is received. if in addition either of the akr_sm_en or xaui_en bits in the respective mdio registers at addresses [3,4].c001?h is set (see table 64 and table 81, these idles will be sequenced on transmission into a pseudo-rando m pattern of ||a||, ||k||, and ||r|| codes according to the ieee 802.3 ae specified algorithm. if neither of the akr_sm_en and xaui_en bits are set, the internal idles will all be transmitted as /k/ codes. elasticity will be achieved by adding or deleting columns of internal idles. if neither the trans_en bit nor the xaui_en bit is set (for either the pcs or the phy xs), the incoming xaui idle codes will all be decoded to the appropriate xgmii control code values in the respective internal fifo. if the akr_en or xaui_en bits are set, they will be sequenced into a pseudo-random pattern of ||a||, ||k||, and ||r|| codes and retransmitted, if not, the in ter packet gap (ipg) will be retransmitted as the same xaui codes as in the first full idle column. for most applications, the xaui_en bit high configuration is the most desirable, and is the default. table 1. valid 10b/8b decoder & encoder patterns receiving serdes internal data transmitting serdes notes serial code, character trans _ en bit (4) e-bit k-bit internal fifo data akr _ sm_ en (4) serial character serial code description valid data x 0 0 0-ff?h x see 802.3 table valid data same data value as received /k/ (sync) k28.5 1 0 1 07?h (2) 1 /a/ /k/ /r/ ieee802.3ae algorithm 001bc (1) 0 /k/ k28.5 comma (sync) /a/ (align) k28.3 1 0 1 07?h (2) 1 /a/ /k/ /r/ ieee802.3ae algorithm 0017c (1) 0 /a/ k28.3 align /r/ (skip) k28.0 1 0 1 07?h (2) 1 /a/ /k/ /r/ ieee802.3ae algorithm 0011c (1) 0 /r/ k28.0 alternate idle (skip) /s/ k27.7 x 0 1 fb 1 /s/ k27.7 start /t/ k29.7 x 0 1 fd 0 /t/ k29.7 terminate k28.1 x 0 1 3c x k28.1 extra comma /f/ k28.2 x 0 1 5c x /f/ k28.2 signal ordered_set /q/ k28.4 x 0 1 9c x /q/ k28.4 sequence ordered_set k28.6 x 0 1 dc x k28.6 k28.7 x 0 1 fc x k28.7 repeat has false comma k23.7 x 0 1 f7 x k23.7 /e/ k30.7 x 1 1 fe x /e/ k30.7 error code any other x 1 = error reg. (3) x invalid code error code note (1): first incoming idle only, subsequent idles in that block repeat first received code. note (2): default value, actually set by ?internal idle? register, [3:4].c003?h, see table 67 and table 83. note (3): value set by ?error code? register, [3:4].c002?h, se e table 66 and table 66. the xaui_en bit forces it to 1fe?h. note (4): if the xaui_en bit is set, the bbt3821 acts as though both the trans_en and akr_en bits are set. bbt3821
13 10 bit mode if a pcs or phy xs 8b/10b codec is inactive (the respective xaui_en and codecena bits are disabled, see table 63/table 64 & table 80/table 81), no 8b/10b coding or decoding is performed. the incoming bits will be arbitrarily split into 10 bit bundles in the internal fifo, optionally based on any commas received, but otherwise not checked, and must be retransmitted in the same clock domain, since no elasticity is possible. therefore the local reference clock must be frequency synchronous with the data source. only the jitter domain will be reset. system designers must en sure that the data stream is adequately dc-balanced and contains sufficient transition density for proper operation, including synchronization. error indications an equivalent schematic of the various ieee-defined and vendor specific fault and status registers in the bbt3821 is shown in figure 4. those register signals that also contribute to the lasi system are indi cated (see figure 5). loss of signal if the reference clock is missing or at an out-of-range frequency, the pll in the cmu will fail to lock. this is the only possible internal cause of a pma ?tx local fault ? indication in bit 1.8.11 (table 10), and will cause ?rx local fault? in bit 1.8.10 and other consequent fault indications (see table 6, table 27 and table 28). loss of the input signal may be caused by poor connections, insufficient voltage swings, or excessive channel loss. if any of these conditions occurs, the loss of signal (los) and (cx4) sig_det detector outputs on the lane will indicate the fault, and may be monitored via the mdio system (see table 6, table 10, table 27, table 28, table 76 and table 77). see also the section on ?loss of signal detection, termination & equalization? on page 9 above. in addition, the mdio mf_sel and mf_ctrl register bits (address 4.c001?h, see table 81) may be set to provide the los/sig_det indication on the mf[3:0] pins. byte or lane synchronization failure the mdio system can i ndicate a failure to achieve byte synchronization on any lane, in the pcs register bits 3.24.3:0 (table 61) or in the phy xs register bits 4.24.3:0 (table 78), which shows the lane-by-lane byte sync status. a failure here, if not caused by any of the above ?loss of signal? conditions, would normally reflect a very high bit error rate, or incorrectly coded data. failure of lane synchronization is indicated for the pcs by register bit 3.24.12 (table 61) or for the phy xs by register bit 4.24.12 (table 78), and can be caused by failure to detect /a/ characters on every lane of a channel, by excessive skew between /a/s on the lanes of a channel, or by inconsistent skews. channel fault indications any of the above faults (los/sig_det, byte sync, or lane align), will (by default) cause a local fault in the relevant receiver. if the pcs_sync_en bit at address [3,4]c000?h (or the xaui_en bit at [3:4].c001?h) (see table 63 to table 65 and/or table 80 to table 81) is set, the internal fifos will propagate the local fault indication specified in the ieee802.3ae-2002 specification (sections 46.3.4 and 48.2.4.2) as the sequence ordered_set ||lf|| (see table 48-4), /k28.4/d0.0/d0.0/d1.0/, whic h will be transmitted as the appropriate xaui or lx4/cx4 tx output. the bbt3821 lanes 0-3 must be connected to xaui and lx4/cx4 lanes 0-3 in strict order. any sequence ordered_set (including ||lf|| and ||rf||) received on an input channel will be retransmitted unchanged on the appropriate output channel. coding violation, disparity & fifo errors the 8b/10b decoder will detect any code violation, and replace the invalid character by the error character /e/. in the case of a disparity error, the error may be propagated and only flagged at the end of a packet (according to the ieee 802.3 rules). the bbt3821 will handle this according to those rules. in addition, the mdio system includes a flag, in registers [3,4].c007?h on bits 11:8 (see table 69 and table 88). similarly, an error in the pcs or phy xs elastic (clock compensation) fifos will be flagged in bits 7:4 of the same registers. the fifo errors may also be flagged on the mf[3:0] pins via the mdio mf_sel and mf_ctrl register bits (address 4.c001?h, see table 81). if a pcs or phy xs 8b/10b codec is inactive, disparity error and coding violation errors do not apply, and the fifos have no active error source. loopback modes in addition to the ieee 802.3ae-required loopback modes, the bbt3821 provides a number of additional modes. each mode is described in detail below, by reference to the detailed functional block diagram in figure 2, together with the register bits controlling it. pma loopback (1.0.0 & 1.c004.[11:8]) the pma loopback is implement ed from the output of the tcx[3:0] serializers to the inpu t multiplexers in front of the rcx[3:0] cdrs. all four lanes are controlled by bit 1.0.0, while the individual lanes can be controlled (one at a time) by the 1.c004?h.[11:8] bits. assuming that this is the only loopback enabled, and that the bist and test pattern generation features are not enabled, the signal flow is from the rxp[3:0][p/n] pins through almost all the ?egress? channel to the input of the (still active) tcx[3:0] output drivers, then (bypassing the rcx[3:0][p/n] inputs, the equalizers and los detectors) back from the cdrs through almost all the ?ingress? channel to the txp[3:0][p/n] pins. bbt3821
14 phy xs (serial) loopback (4.0.14 & 4.c004.[11:8]) the phy xs loopback is implement ed from the output of the txp[3:0] serializers to the input multiplexers in front of the rxp[3:0] cdrs. all four lanes are controlled by bit 4.0.14, while the individual lanes can be controlled (one at a time) by the 4.c004?h.[11:8] bits. assuming that this is the only loopback enabled, and that the bist and test pattern generation features are not enabled, the signal flow is from the rcx[3:0][p/n] pins through almost all the ?ingress? channel to the input of the (still active) txp[3:0] output drivers, then (bypassing the rxp[3:0][p/n] inputs, the equalizers and los detectors) back from the cdrs through almost all the ?egress? channel to the tcx[3:0][p/n] pins. pcs parallel network loopback (3.c004.[3:0]) this loopback is implemented (at the internal xgmii-like level) from the output of the rxfifos in the ?ingress? channel to the input of the txfifos in the ?egress? channel. the individual lanes can be controlled (one at a time) by the 3.c004?h.[3:0] bits. assuming that this is the only loopback enabled, and that the bist and test pattern generation features are not enabled, the signal flow is from the rcx[3:0][p/n] pins through the pma/pmd and pcs and again pma/pmd to the tcx[3:0][p/n] pins. this coul d also be seen as a ?short? loopback at the xgmii input of the phy xs. pcs (parallel) loopback (4.c004.[3:0] & optionally 3.0.14) this loopback is implemented (at the internal xgmii-like level) from the output of the rxfifos in the ?egress? channel to the input of the txfifos in the ?ingress? channel. the individual lanes can be controlled (one at a time) by the 4.c004?h.[3:0] bits. if the enable bit in 3.c001.7 (table 64) is set, all four lanes can be controlled by bit 3.0.14. since the latter is specifically exclu ded by subclause 45.2.3.1.2 of the ieee 802.3ae-2002 specification for a 10gbase-x pcs, the default is to not enable this loopback bit, and if it is enabled, the bbt3821 does not conform to the ieee specification. a maintenance request has been s ubmitted to the ieee to enable this loopback bit as optional, and to allow a ?pcs loopback capability? bit in register bit 3.24.10 (see http://www.ieee802.org/3/maint/requests/maint_1113.pdf ), but this has so far been rejected, and may never be approved. assuming that this is the only loopback enabled, and that the bist and test pattern generation features are not enabled, the signal flow is from the rxp[3:0][p/n] pins through the full phy xs via the internal xgmii to the txp[3:0][p/n] pins. this could also be seen as a ?short? loopback at the xgmii input of the pcs. pll lock fail ieee reg 1.8.11 see lasi txfault ieee reg 1.1.7 ieee reg 1.8.10 see lasi ieee reg 1.10.0 ieee reg 1.10.4:1 cx4 lx4 oprlos [3:0] reg 1.c00a.7:4 reg 1.c01d.6 pcs byte sync pcs lane align ieee reg 3.1.2 phy xs byte sync phy xs lane align ieee reg 3.1.7 ieee reg 3.8.11 ieee reg 3.8.10 see lasi see lasi ieee reg 3.24.3:0 ieee reg 3.24.12 ieee reg 4.1.7 ieee reg 4.8.11 ieee reg 4.8.10 see lasi see lasi ieee reg 4.24.12 ieee reg 4.1.2 ieee reg 4.24.3:0 reg 4.c00a.3:0 phy xs signal detect pma/pmd signal detect reg 1.c00a.3:0 cx4 signal_ detect reg 1.c001.10:8 level reg 3.c001.10:8 level cx4 lx4 ieee reg 1.1.2 reg 1.c012h.13 polarity see lasi see lasi figure 4. ieee and vendor specif ic fault and status registers (equivalent schematic) bbt3821
15 serial test loopbacks (1.c004.12 & 4.c004.12) in addition to the above loopbacks, the bb t3821 also offers two serial loopbacks directly between the serial inputs and outputs. these loopbacks use th e recovered clock as the timing for the outputs (instead of the multiplied reference clock), so do not reset the jitter or clock domains, and in addition do not provide any pr e-emphasis on the outputs. furthermore, on the pma/pmd side (1.c004.12) the lanes are internally swapped (so the lane 3 output is from the lane 0 input, etc.). because of their limited utility, they are not illustrated in figure 2 or figu re 6. they are mainly useful for debugging an otherwise intr actable system problem. the reference clock still needs to be within locking range of the input frequency. the remainder of the signal path will remain active (as normal), so that if for example 1.c004.12 is set, data coming in on rcx[3:0], in addition to emerging on tcx[0:3] without retiming, et c., will also emerge from txp[3:0] retimed, as usual. serial management interface the nliten bbt3821 implements the mmd management interface defined in i eee 802.3-2002 clauses 22 & enhanced in ieee 802.3ae-2002 clause 45. this two-pin interface allows serial read/write of the internal control registers and consists of the mdc clock and mdio data terminals. the padr[4..0] pins are used to select the ?port address? to which a given nliten bbt3821 device responds. the bbt3821 will ignore clause 22 format frames (on a frame-by-frame basis), based on the second st (start) bit value. the two formats are shown in table 3, together with the references to the respecti ve ieee 802.3 specifications. mdio register addressing the padr[4..0] hardware addres s pins control the prtad (port address) value, each port normally consisting of a series of mdio managed devices (mmds). each port may include up to 31 different devices, of which the current specification defines 8 types, and allows vendor specification of two others. the bbt3821 device corresponds to the pma/pmd, pcs and phy xgxs defined types, so responds to devad values of 1, 3 and 4 respectively. the clause 45-accessible registers are listed for each device address in the tables referenced in table 2. many of these register addr esses are ieee-defined; the ?vendor defined? registers are arranged to be as devad independent as possible. each individual device may have up to 2 16 (65,536) registers. the bbt3821 implements all the defined registers for 10gbase pma/pmd, 10gbase-x pcs and phy xs devices, and a few vendor specific registers for each devad respectively. the latter have been placed in the blocks beginning at d.c000?h so as to avoid the areas currently defined as for use by the xenpak module and similar msa devices, to facilitate use of the bbt3821 in such modules and systems. table 2. devad device address table devad value ieee definition register list table devad = 1 (00001?b) pma/pmd device table 4, page 19 devad = 3 (00011?b) pcs device table 56, page 38 devad = 4 (00100?b) phy xs (xgxs) device table 74, page 45 table 3. mdio management frame formats clause 22 format (from table 22-10 in i eee std 802.3-2002 edition, for reference) opern pre st op phyad regad ta data idle read 1?.1 01 10 ppppp rrrrr z0 dddddddddddddddd z write 1?.1 01 01 ppppp rrrrr 10 dddddddddddddddd z clause 45 format (from table 45-64 in ieee 802.3.ae-2002) opern pre (1) st op prtad devad ta address/data idle addrs 1?.1 00 00 ppppp ddddd 10 aaaaaaaaaaaaaaaa z write 1?.1 00 01 ppppp ddddd 10 dddddddddddddddd z (2) read 1?.1 00 11 ppppp ddddd z0 dddddddddddddddd z read inc 1?.1 00 10 ppppp ddddd z0 dddddddddddddddd z note (1): the ?preamble? consists of at least 32 bits. after a software reset, a few extra preamble bits may be needed, dependin g on the mdc clock rate. see timing diagrams in figure 15 and figure 17. note (2): the actual register will not be updated until up to three additional mdc cycles have been received. see figure 15. bbt3821
16 i 2 c space interface in addition to the standard mdio registers discussed above, the bbt3821 implements the register addresses specified in the xenpak msa specification for the nvr, dom and lasi blocks. the built-in i 2 c controller can be configured to load these registers with the msa-sp ecified data on start-up or reset or on demand from an i 2 c eeprom (frequently included as part of a dom circ uit) and/or one or four dom circuits (see below). optionally, a portion of the nvr space may be used to autoload the various bbt3821 control registers at start-up or reset. these operations are discussed in more detail below. nvr registers & eeprom if the xp_ena pin is asserted enabled (high), at the end of hardware reset or power-up the bbt3821 will attempt to load the nvr area by initiating a nvr-block read through the 1.32768 (1.8000?h) control register (table 15). see figure 18. the same will occur if the appropriate command value is written into this register. the i 2 c interface will attempt to read the a0.00:ff?h i 2 c space into the 1.8007:8106?h mdio register space. the command status bits in the 1.32768 (1.8000?h) control register will reflect the status of this operation. failure may occur if the expected ack is not received from any address after the number of attempts set in control regist er 1.32273 (1.8005?h), default 63 (table 20), or if a collision is detected on the i 2 c bus. the timing sequence of this block read operation is shown in figure 20. the host can check the checksums against the values at 1.807d, and optiona lly 1.80ad and 1.8106, and take appropriate action. as soon as the xenpak mdio space is loaded, the sta mdio device may interrogate it. note that the bbt3821 merely stores the values read from the eeprom or other device at a0.00-ff?h, and, with a few exceptions, does not interpret them in any way. the exceptions are listed ex plicitly in table 22, together with the other uninterpreted groups, and are: ? the package oui at 1.32818: 32821 (1.8032:5?h), which will be mirrored in the ieee-defined 1.14:15 (1.e:f?h) space, as required by sectio n 10.8.2 of the xenpak spec; the allowable values here are specified by the xenpak, xpak and x2 specifications; ? the dom capability byte at 1.32890 (1.807a), see the dom registers section, page 16; ? the auto-configure size and pointer bytes at 1.33028:9(1.8104:5) ; (see auto-configuring control registers, page 16). ? if the auto-configure operation is enabled, the block of bytes so specified will be written into the bbt3821 control registers, (see auto-config uring control registers on page 16 and table 92). other registers may be interpreted in future versions of the bbt3821. auto-configuring control registers if the xp_ena pin is asserted, and the i 2 c controller can successfully read the i 2 c nvr space into the mdio nvr space, the bbt3821 will examine the auto-configure pointer value at 1.33029 (1.8105?h). if this is neither 00?h or ff?h, the bbt3821 will use that value ( s below) as an offset pointer into th e a0.00:ff?h i 2 c space already copied into the mdio nvr space, and the number of bytes given in the auto-configure size register 1.33028 (1.8104) value (n below) to load n bytes from the nvr data starting from location s into the various bbt3821 configuration control registers. the loading sequence and the correspondence between the nvr block and the control registers is listed in table 92. the auto-configure engine will behave benignly if the s and n values are misconfigured, so that if s + n 252 (for example), the auto-configure block will stop at an s + n value of 252, and not use s , n , or the checksum value to load a configuration control regi ster. (hence the exclusion of ff?h as a value for s is no limitation). similarly, values of n > 40 will be ignored. note that in a xenpak/xpak/x2 module, the value of s should not be between 00?h and 76?h, since this would start the loading from within the msa-defined region. (hence the exclusion of 00?h as a value for s is normally no limitation). if the value of s lies between 77?h and a6?h, that portion of the auto-configure data within that band can be overwritten as part of the customer writable area defined by the msa specifications; if this is undesirable, that range of values should also be excluded. on the other hand, this could be used to allow some customization for specific end-use r configuration values. if the block overlaps the boundary between the ?customer writable? and ?vendor specific? areas, t he first part would be customer- writable, and the second part not. the order of the configuration registers has been arranged to place those most likely to be useful in such a customer-con figuration environ ment at the beginning of the block. the ?c ustomer area checksum? would be part of the auto-configure block, and some other byte in the ?customer writeable area? would need to be adjusted to make the checksum and the desired configuration value coincide. the command status bits in the nvr command register (table 15) at 1.32768.3:2 (1.8000 ?h.3:2) will reflect the success of both the nvr and (if called for) the auto-configure loading operations. dom registers if the nvr load operation su cceeds, the (newly read-in) xenpak register at 1.32890 (1.807 a?h) is examined, and if the dom capability bit is set (bit 6, see table 23), the i 2 c interface will attempt to read the dom values from the i 2 c device address space specified in the same register (bits 2:0), normally 001?b pointing to a2?h. see note (2) to table 23 for details. a full block of data will be read from this space (normally a2.00:ff?h) into the 1.40960:41215 (1.a000: a0ff?h) mdio register dom space. see figure 18 and figure 20 for details. the dom control register is implemented in the bbt3821 at bbt3821
17 1.41216 (1.a100?h), so that one-ti me or (by default) periodic updates of the dom information can be loaded into the mdio dom space by writing the appropriate values into it, as shown in table 38, page 33. the actual automatic update rates selectable in this xenpak-defined register are controlled by the dom control register in the bbt3821 vendor-specific register space at 1.49176 (1.c01 8?h), which also controls other actions of the dom interface (see table 51). in particular, since many available dom circuits can handle only one lane, bit 2 enables or disables indirect access to separate dom circuits on the four lanes. if the bit is 0? b, the dom circuit is directly addressed at ax.00:ff?h, and is assumed to provide the full four lane data, including the determination of which data is to be treated as the ?furthest out of range? or the ?representative value?, as specified in note 1 to table 27 in section 11.2.6 of the xenpak r3.0 specification, to be returned in the xenpak- defined 1.a060:a06d?h space for a wdm module. if bit 2 of 1.c018?h is set to 1?b, the dom data is polled from four devices attached to the i 2 c serial bus, getting 10 bytes from each of them. the 40 bytes of data are stored in the four lane register blocks starting from 1.a0c0?h, 1.a0d0?h, 1.a0e0?h and 1.a0f0?h respectively. the device addresses of these four dom devices on the 2-wire bus are configured by registers 1.c01b?h and 1.c01c?h (table 54); the starting memory addresses by registers 1.c019?h and 1.c01a?h (table 53). since the bbt3821 has no mechanism to determine out-of- range data, it chooses one of these four 10-byte long groups of data to copy into 1.a060?h:a069?h according to bits 1:0 of 1.c018?h (the ?representative? lane per the above-mentioned xenpak note). in addition, the alarm and status flags (table 36 and table 37) will be loaded from this lane into 1.a070:a075?h. the bbt3821 assumes that the dom circuit(s) will have these a/d values and flags at the same relative offsets as those specified in the xe npak r3.0 and the sff-8472 specifications. general purpose (gpio) pins the bbt3821 includes some flexibly configurable general purpose input-output (gpio) pins, which may be configured to be inputs or outputs. as inputs, their level may be read directly via the mdio system, but also they may be configured (again via mdio re gisters, see table 47 through table 50) to optionally trigger the lasi on either a high or low level. the gpio pins may also individually be used as outputs, and set high or low, under mdio control. the gpio control registers are among those that can be auto- configured on start-up. lasi registers & i/o the bbt3821 implements the link alarm status interrupt (lasi) interface defined in section 10.13 of the xenpak specification. the source and nature of these is described above under ?error indications? on page 13 and in figure 4. in addition to these specification-defined inputs, the bbt3821 incorporates a number of additional inputs, related to the possible byte alignment and 8b/10b code violations, which may be used to trigger a lasi. the available inputs depend on the lx4/cx4 select lx4_mode pin (table 99), and are detailed in table 27 and table 28, and include: 1. various status bits within the bbt3821, derived from its operations; in particular, the los indications, byte sync and efifo errors, the fault bits [1,3,4].8.10:11, etc. 2. the optical interface status pins (in lx4 mode), see table 99. 3. the alarm flags in 1.a070:1 (table 36). these bits are gated with the enable bits in 1.9006:7 (table 30 and table 31) and the lx4/cx4 lx 4_mode pin (table 99) to drive bits 1.9004.1 & 1.90 03.1 (table 28 & table 27). 4. the gpio pins (table 100). if configured as inputs, they may be used to optionally trigger the lasi on either a high or low level. see above. these status inputs can all be read via the lasi status registers (1.9003 to 1.9005, see table 27 to table 29). any of these inputs, if enabled via the lasi control registers, 1.9000 to 1.9002 (table 24 to table 26), can drive the lasi pin. figure 5 shows an e quivalent schematic for the lasi system (an expansion of figure 21 in the xenpak specification). reading additional eeprom space via the i 2 c interface the i 2 c interface will allow single-byte reads from any possible i 2 c address. the device address and memory address are written into the 1.32769 (1.8001?h) and 1.32770 (1.8002?h) registers respectively (see table 16 and table 17), and on issuing a ?read one byte? command (write 0002?h to 1.32768 = 1.8000?h) t he data will be read from the i 2 c space in the mdio register at 1.32771 (1.8003?h, see table 18). for timing sequence, see figure 22. note that a 16-bit addressable eeprom (o r equivalent) device on the i 2 c bus may be read by setting the long memory bit 1.32773.8 (1.8005.8?h) to a ?1?, and writing a full 16-bit memory address value into 1.32770 (1.8002?h). this in principle allows access to almost a full 8mb of i 2 c space, excluding only the nvr and (optional) dom device address portions. this 16-bit operat ion must not be used on an 8-bit device, since the register address setting operation will attempt to write the low byte of the address into the register at the high byte address. such a 16-bit memory address device should be located at a device address not used by the nvr or dom system. these one-byte operations could be used to read other types of data from (multiple) dom devices (such as limit lookup tables), or for expanded informational areas. it also facilitates the use of i 2 c-based dcp (digital control potentiometer) devices for laser current control, and other similar setup and monitoring uses. bbt3821
18 d clk clr ls_alarm lasi ls alarm masked tx alarm masked rx alarm masked gpio alarm masked tx_alarm register 1.9003h.[6:0] rx_alarm_status register 1.9004h.[10:0] tx_alarm_status latch on high clear on read reg 4.8.11 cx4 lx4 lx4 cx4 lx4 cx4 lx4 cx4 reg 3.8.11 reg 1.8.11 optx lop opt temp optx lbc cx4 lx4 cx4 lx4 cx4 lx4 reg 1.a070h[7:0] tx_flag reg 1.9006h[7:0] tx_flag control q clock on any change link status reg. 1.10.0 reg. 3.24.12 reg. 4.24.12 clear on read of 1.9005 reg 1.9002h[3:0] lasi control reg 1.9005h[3:0] lasi status register 1.9001h[10:0] tx_alarm control register 1.9000h[6:0] rx_alarm control reg 4.8.10 rx_flag reg 1.a074h[7:6] rx_flag reg 1.9007h[7:6] rx_flag control lx4 cx4 reg 3.8.10 reg 1.8.10 cx4 lx4 oprx op reg 1.10.0 reg 1.c01dh.3 latch on high clear on read gpio [4:0] reg 1.c012h.[12:8] gpio polarity reg 1.c012h.[4:0] gpio-lasi en reg 1.c01dh.2:0 alarm pin polarity reg 1.c011h.[12:8] gpio input latch hi legend selector for cx4 vs lx4 external pad lx4 cx4 lasi change rx_alarm gpio->lasi reg 1.c012h.13 polarity tx_ fault phy xs byte synch reg. 4.24.3:0 reg. 4.c00ah. 3:0 phy xs los (sig det) reg. 4.c007h. 11:8 phy xs fifo error reg. 4.c007h. 7:4 phy xs code error tx_flag reg 3.24 [3:0] pcs byte synch reg. 3.c007h. 11:8 pcs fifo error reg. 3.c007h. 7:4 pcs code error see ieee figure 5. lasi equivalent schematic (see also figure 4) bbt3821
19 writing eeprom space through the i 2 c interface the bbt3821 permits two method s for writing the requisite values into eeprom or other i 2 c devices from the mdio space into the i 2 c register space. many dom circuits protect their important internal data through some form of password protection, and in general the bbt3821 will allow this to be done without a problem. block writes to eeprom space the first method is applicable only to the nvr space (i 2 c address space a0.00:ff?h). if the wrtp (write protect) pin is inactive (low), and the nvr write size bit (1.32773.7 = 1.8005.7?h) is set to a ?1?, then issuing a ?write all nvr? command (write 0023?h to 1.32768 = 1.8000?h) will write the current contents of mdio regi sters 1.8007:8106?h into the nvr space. the ?nvr write page size? bits in 1.32773.1:0 (1.8005.1:0?h) control the bloc k size used for the write operation. see figure 21 for the sequence timing. normally this operation is only useful for init ialization of a module eeprom space, but it could be used for fi eld upgrades or the like. if the wrtp (write protect) pin is high (active, normal condition), or the write size bit (1.32773.7 = 1. 8005.7?h) is cleared to a ?0?, then issuing a ?write all nvr? command (write 0023?h to 1.32768 = 1.8000?h) will write onl y the current contents of the mdio register block within 1.807f:80ae?h to the xenpak- defined customer area, a0.77:a6?h. the actual block write will occur one byte at a time. the block write size controls cannot be used here, since the customer area block boundaries do not lie on page-write boundarie s of the eeprom, a feature of the xenpak specification. byte writes to eeprom space the second method is applicable to any part of the i 2 c space. the write operation is performed one byte at a time. the device address and memory address are written into the 1.32769 (1.8001?h) and 1.32770 (1.8002?h ) registers respectively (see table 16 and table 17), and the data to be written into the 1.32772 (1.8004?h) register. on issuing a ?write one byte? command (write 0022?h to 1.32768 = 1.8000?h) the data will be written into the i 2 c space. see figure 23 for the timing sequence. note that if the wrtp (write protect) pin is high, or the write size bit (1.32773.7 = 1. 8005.7?h) is cleared to a ?0?, writes to any part of the ba sic nvr space outside the xenpak- defined customer area will be igno red. also note that a 16-bit addressable eeprom (or equivalent) device on the i 2 c bus may be written by setting the long memory bit 1.32773.8 (1.8005.8?h) to a ?1?, and writin g a full 16-bit memory address value into 1.32770 (1.8002?h). no te that this 16-bit operation must not be used on an 8-bit device. these one-byte operations could be used to load modified device address values or protective passwords into multiple dom devices, or for loading other types of data into them. they are also useful for writing data into i 2 c interface dcp devices for setting laser currents, etc. mdio registers in the following tables, the addresses are given in the table headers both in decimal (as us ed in the ieee 802.3ae and 802.3ak documents) and in hexadecimal form. where the registers coincide in structure and meaning, but the device addresses differ, the underlying register bits are the same, and may be read or written indiscrimi nately via any re levant device address. for instance a full reset may be initiated by writing any one of 1.0.15, 3.0. 15, or 4.0.15. while the reset is active, reading any of these bits would return a ?1? (except that the reset lasts less than the mdio preamble plus frame time). when the reset operation is complete, reading any of them will return a ?0?. note that extra preambles may be required after such a software reset (see figure 17). table 4. mdio pma/pmd devad 1 registers pma/pmd device 1 mdio registers address name description default ac (5) r/w details dec hex 1.0 1.0 pma/pmd control 1 reset, enable serial loop back mode. 2040?h r/w table 5 1.1 1.1 pma/pmd status 1 local fault and link status 0004?h (2) ro/ll table 6 1.2:3 1.2:3 id code manufacturer oui & device id 01839c6v?h ro see (1) 1.4 1.4 speed ablty pma/pmd speed ability 0001?h ro table 7 1.5 1.5 dev in pkg. devices in package, clause 22. 001a?h ro table 8 1.6 1.6 vend sp dev vendor specific devices in package 0000?h ro table 8 1.7 1.7 pma/pmd control 2 pma/pmd type selection p (4) ro (6) ta b l e 9 1.8 1.8 pma/pmd status 2 fault summary, device ability b311?h (2) ro (lh) ta b l e 1 0 1.9 1.9 pmd tx dis disable pmd transmit 0000?h r/w table 11 1.10 1.a pmd sig det pmd signal detect 001f?h (2) ro table 12 bbt3821
20 note (1): v? is a version number. see ?jtag & ac-jtag o perations? on page 53 for a note about the version number. note (2): read values depend on status signal values. values shown indicate ?normal? operation. note (3): if nvr load operation succeeds, will be overwritten by value loaded, see table 22. note (4): default value depends on cx4/lx4 select lx4_mode pin value. note (5): for rows with ?a?, the default value may be overwritten by the auto-configure operation (see ?auto-configuring control registers? on page 16 and table 92 for details). note (6): ieee 802.3 shows as r/w, but cannot write any other value than that set by lx4_mode pin. 1.11 1.b pmd ext ca pmd extended capability 0001?h ro table 13 1.14:15 1e:f pkg oui pmd package oui, etc. 00000000?h (3) r/w table 14 1.32768 1.8000 nvr cntrl nvr control & status register 0003?h r/w table 15 1.32769 1.8001 i 2 c dev ad 1-byte operation device addr. a2?h r/w table 16 1.32770 1.8002 i 2 c mem ad 1-byte operation memory addr. 0000?h r/w table 17 1.32771 1.8003 i 2 c rd data 1-byte operation read data 0000?h ro table 18 1.32772 1.8004 i 2 c wr data 1-byte operation write data 0000?h r/w table 19 1.32773 1.8005 i 2 c op ctl i 2 c operation control 004d?h r/w table 20 1.32774 1.8006 i 2 c op stts i 2 c operation status 0000?h ro/lh table 21 1.32775: 33030 1.8007: 8106 nvr copy registers xenpak nvr register copies set by eeprom r/w table 22 1.36864 1.9000 rx al ctrl rx alarm control see table (4) ar/wtable24 1.36865 1.9001 tx al ctrl tx alarm control see table (4) ar/wtable25 1.36866 1.9002 lasi ctrl lasi control 0000?h a r/w table 26 1.36867 1.9003 rx al stts rx alarm status 0000?h (2) ro table 27 1.36868 1.9004 tx al stts tx alarm status 0000?h (2) ro table 28 1.36869 1.9005 lasi stts lasi status 0000?h (2) ro table 29 1.36870 1.9006 dom tx dom tx_flag control 0000?h a r/w table 30 1.36871 1.9007 dom rx dom rx_flag control 0000?h a r/w table 31 1.40960: 41215 1.a000 :a0ff dom copy registers alarm & warning thresholds, a/d values, (cf sff-8472) set by dom devices ro table 32: ta b l e 3 7 1.41216 1.a100 dom ctrl dom control & status 0000?h r/w table 38 1.49153 1.c001 pma ctrl2 pma control 2 0000?h a r/w table 39 1.49156 1.c004 pma lb pma loopback control 0000?h a r/w table 40 1.49157 1.c005 pma pre pma pre-emphasis control see table (4) ar/wtable41 1.49158 1.c006 pma eql pma equalizer boost control see table (4) ar/wtable43 1.49162 1.c00a sig_det signal detect flags 0000?h (2) ro table 44 1.49163 1.c00b fine tune adjust pre-emphasis, amplitude see table (4) ar/wtable45 1.49167 1.c00f soft rst soft reset 0000?h r/w table 46 1.49168: 49171 1.c010 :c013 gpio cnfg gpio config, status & alarm registers 0000?h (2) a r/w table 47: ta b l e 5 0 1.49176 1.c018 dom control dom control register 0000?h a r/w table 51 1.49177:8 1.c019:a dom mem dom indirect start addresses 6060?h a r/w table 53 1.49179:80 1.c01b:c dom dev dom indirect de vice addresses see tables a r/w table 54 1.49181 1.c01d statuspolrty lasi alarm pin polarity 0000?h a r/w table 55 table 4. mdio pma/pmd devad 1 registers (continued) pma/pmd device 1 mdio registers address name description default ac (5) r/w details dec hex bbt3821
21 ieee pma/pmd registers (1 .0 to 1.15/1.000f?h) note (1): after this reset bit is writte n, the bbt3821 will not begin c ounting preamble bits immediately. see figure 17 for detai ls. note (1): this bit is latched low on a detected fa ult condition. it is set high on being read. table 5. ieee pma/pmd control 1 register mdio register address = 1.0 (1.0000?h) bit(s) name setting default r/w description 1.0.15 3.0.15 4.0.15 reset 1 = reset 0 = reset done, normal operation 0?b r/w sc writing 1 to this bit will reset the whole chip, including the mdio registers. (1) 1.0.14 reserved 0?b 1.0.13 speed select 1 = 10gbps 1?b ro 1 = bits 5:2 select speed 1.0.12 reserved 0?b 1.0.11 lopower 0 = normal power 0?b r/w no low power mode, writes ignored 1.0.10:7 reserved 0?h 1.0.6 speed select 1 = 10gbps 1?b ro 1 = bits 5:2 select speed 1.0.5:2 speed select 0000 = 10gbps 0?h ro operates at 10gbps 1.0.1 reserved 0?b 1.0.0 pma loopback 1 = enable loopback 0 = normal operation 0?b r/w enable serial loop back mode on all four lanes, xaui in to xaui out. table 6. ieee pma/pmd status 1 register mdio register address = 1.1 (1.0001?h) bit name setting default r/w description 1.1.15:8 reserved 00?h 1.1.7 local fault 1 = pma local fault 0?b ro derived from register 1.8.11:10 1.1.6:3 reserved 0?h 1.1.2 rx link up 1 = pma rx link up 0 = pma/d rx link down 1?b (1) ro ll (1) ?up? means cx4/lx4 signal level is ok, and the pll locked 1.1.1 lopwrable low power ability 0?b ro device does not support a low power mode 1.1.0 reserved 0?b table 7. ieee pma/pmd, pcs, phy xs, speed ability register mdio register addresses = 1.4, 3.4 & 4.4 ([1,3,4].0004?h) bit name setting default r/w description 1.4.15:3 3.4.15:2 4.4.15:1 reserved for future speeds 000?h 1.4.2:1 3.4.1 10pass-t2/ 2base-tl efm ability 00?b ro device cannot operate @ 2base-tl or 10pass- t2 1.4.0 3.4.0 4.4.0 10gbpsable 10gbps ablility 1?b ro device able to operate @ 10gbps bbt3821
22 note (1): value depends on the current state of the lx4/cx4 select lx4_mode pin. although ieee 802.3ae specifies r/w bits, only valid values may be written; since the pin controls the available valid value, no meaningful write is possible. table 8. ieee devices in package registers mdio register addresses = 1.5, 3.5, 4.5 ([1,3:4].0005?h) bit name setting default r/w description [1,3:4].5.15:8 reserved 000?h [1,3,4].5.7 link partner link partner pma/ pmd present 0?b ro device has no link partner [1,3,4].5.6 10pass-ts tone table 10pass-ts tone tabl e present 0?b ro device has no 10pass-ts tone table [1,3:4].5.5 dte xs dte xs present 0?b ro device ignores devad 5 [1,3:4].5.4 phy xs phy xs present 1?b ro device responds to devad 4 [1,3:4].5.3 pcs pcs present 1?b r o device responds to devad 3 [1,3:4].5.2 wis wis present 0? b ro device ignores devad 2 [1,3:4].5.1 pmd_pma pmd/pma present 1?b ro device responds to devad 1 [1,3:4].5.0 cls_22 clause 22 register s 0?b ro device ignores clause 22 mdio register addresses = 1.6, 3.6, 4.6 ([1,3:4].0006?h) [1,3:4].6.15 vndrdev2 vendor specific dev2 0?b ro device ignores devad 31 [1,3:4].6.14 vndrdev1 vendor specific dev1 0?b ro device ignores devad 30 [1,3,4].6.13 clause 22 extn. clause 22 extens ion 0?b ro device has no clause 22 extension [1,3:4].6.12:0 reserved 000?h table 9. ieee pma/pmd type select register mdio register addresses = 1.7 (1.0007?h) bit name setting default r/w description 1.7.15:4 reserved 000?h 1.7.3:0 pma/pmd type 0100 = 10gbase-lx4 0000 = 10gbase-cx4 p?b (1) ro lx4_mode select pin high is lx4 value, low is cx4 value table 10. ieee pma/pmd status 2 devi ce present & fault summary register mdio register addresses = 1.8 (1.0008?h) bit name setting default r/w description 1.8.15:14 device present 10 = device present 10?b ro when read as ?10?, it indicates that a device is present at this device address 1.8.13 txlocalflt ability 1 = pma/pmd can detect tx fault 1?b ro pma/pmd has the ability to detect a local fault on transmit path 1.8.12 rxlocalflt ability 1 = pma/pmd can detect rx fault 1?b ro pma/pmd has the ability to detect a local fault on receive path 1.8.11 txlocalflt 1 = tx local fault; on egress channel 0?b ro lh (1) pll lock fail (missing refclk) or tx_fault pin active 1.8.10 rxlocalflt 1 = rx local fault; on ingress channel 0?b ro lh (1,2) pll lock fail (missing re fclk), or loss of signal in 1.10 (1.000a?h) 1.8.9 ext ability 1 = extended ability register present. 1?b ro device has extended ability register in 1.11 (1.000b?h) 1.8.8 tx disable 1 = can disable tx 1?b ro device can di sable transmitter 1.8.7 10gbase-sr 0 = cannot perform 0?b ro device cannot be 10gbase-sr 1.8.6 10gbase-lr 0 = cannot perform 0?b ro device cannot be 10gbase-lr bbt3821
23 note (1): these bits are latched high on any fault condition detected. they are reset low (cleared) on being read. they will als o be reset low on reading the lasi registers 1.9003?h (bit 10, see table 27) or 1.9004?h (bit 11, see table 28). note (2): the source of ?loss of signal? depends on the lx4/cx4 select lx4_mode pin (see register 1.10, 12, note (1) below). note (1): in cx4 mode the tcxnp/n pin outputs will be disabled; in lx4 mode only tx_ena[n] pin is disabled. note (1): these bits reflect the oprlos[3:0] pins (table 99) in lx4 mode, or the cx4 signal_detect function in cx4 mode, dependi ng on the lx4_mode select pin. note (1): these values reflect the i eee 802.3ak 10gbase-cx4 specification. 1.8.5 10gbase-er 0 = cannot perform 0?b ro device cannot be 10gbase-er 1.8.4 10gbase-lx4 1 = can perform 1?b ro device can be 10gbase-lx4 1.8.3 10gbase-sw 0 = cannot perform 0?b ro device cannot be 10gbase-sw 1.8.2 10gbase-lw 0 = cannot perform 0?b ro device cannot be 10gbase-lw 1.8.1 10gbase-ew 0 = cannot perform 0?b ro device cannot be 10gbase-ew 1.8.0 pma loopback 1 = can perform 1?b ro device can perform pma loopback table 10. ieee pma/pmd status 2 device present & fault summary register (continued) mdio register addresses = 1.8 (1.0008?h) bit name setting default r/w description table 11. ieee transmit disable register mdio register address = 1.9 (1.0009?h) bit name setting default r/w description 1.9.15:5 reserved 1.9.4 pmd dis 3 disable tx on lane 3 (1) 0?b r/w 1 = disable pmd transmit on respective lane (1) 0 = enable pmd transmit on respective lane (unless txon/off pin is low) 1.9.3 pmd dis 2 disable tx on lane 2 (1) 0?b r/w 1.9.2 pmd dis 1 disable tx on lane 1 (1) 0?b r/w 1.9.1 pmd dis 0 disable tx on lane 0 (1) 0?b r/w 1.9.0 pmd dis all disable tx on all 4 lanes 0?b r/w table 12. ieee pmd signal detect register mdio register address = 1.10 (1.000a?h) bit name setting default r/w description 1.10.15:5 reserved 1.10.4 pmd rx ln 3 pmd signal det?d 1?b (1) ro 1 = pmd signal detected on respective lane (global, all lanes) 0 = pmd signal not detected on respective lane (global, any lane) 1.10.3 pmd rx ln 2 pmd signal det?d 1?b (1) ro 1.10.2 pmd rx ln 1 pmd signal det?d 1?b (1) ro 1.10.1 pmd rx ln 0 pmd signal det?d 1?b (1) ro 1.10.0 pmd rx glob pmd signal det?d 1?b (1) ro table 13. ieee extended pma/pmd capability register (1) mdio register addresses = 1.11 (1.000b?h) bit name setting default r/w description 1.11.15:1 reserved 0000?h ro 1.11.0 (1) 10gbase-cx4 1 = can perform 1?b ro device can be 10gbase-cx4 bbt3821
24 xenpak-defined registers (1.8000?h to 1.8106?h) note (1): user writes to these bits are not valid unless the comma nd status is idle. the command status will not return to idle until read after command completion (either succeed or failed). note (2): at the end of a hardware reset via the rstn pin, on powerup, or on a register [1,3,4].0.15 reset operation, and if the xp_ena pin is asserted, the bbt3821 will automatically begin an ?all nvr read? operation. note (3): the single byte commands are controlled through the bits of the registers at 1.32769:32774 (1.8001:8006?h). the ?block write/read? commands are affected by register 1.32773 (1.8005?h). additional status is available in 1.327743 (1.8006?h) note (1): 8-bit-addressed i 2 c devices are addressed using bits 7:0. never set bit 1.32773.8 (1.8005?h.8) for 16-bit address operation with an 8-bit address i 2 c device. table 14. ieee package identifier registers mdio register addresses = 1.14:15 (1.000e:f?h) bit name setting default r/w description 1.14.15:0 package id package oui bits 3:24 & etc. 00?h r/w if nvr is loaded, these are copies of 1.32818:32819 (1.8032:8033?h) & 1.32820:32821 (1.8034:8035?h) 1.15.15:0 package id 00?h r/w table 15. xenpak nvr control & status register mdio (xenpak) register address = 1.32768 (1.8000?h) bit name setting default r/w description 1.32768.15:6 reserved 000?h r/w 1.32768.5 nvr command (1) 1 = write nvr 0 = read nvr 0?b (2) r/w write/read control for i 2 c operation 1.32768.4 reserved 0?b ro 1.32768.3:2 nvr command status (3) current status of nvr command 00?b ro 11 = command failed 10 = command in progress/queued 01 = command completed with success 00 = idle 1.32768.1:0 extended nvr command nvr operation to be performed 11?b (2) r/w 10 = read/write one byte (3) 11 = read/write all nvr contents (3) other values = reserved table 16. i 2 c one-byte operation device address register mdio register address = 1.32769 (1.8001?h) bit name setting default r/w description 1.32769.15:8 reserved 00?h ro 1.32769.7:0 device address i 2 c device address to access a2?h r/w all i 2 c device addresses are even. bit 0 cannot be set. table 17. i 2 c one-byte operation memory address register mdio register, address = 1.32770 (1.8002?h) bit name setting default r/w description 1.32770.15:0 memory address i 2 c memory address to access 0000?h (2) r/w i 2 c memory address within device address of 1.32769 (1.8001?h) table 18. i 2 c one-byte operation read data register mdio register address = 1.32771 (1.8003?h) bit name setting default r/w description 1.32771.15:8 reserved 00?h ro 1.32771.7:0 read data i 2 c read data 00?h ro result of i 2 c 1-byte read operation bbt3821
25 note (1): this bit should only be set if an i 2 c device which needs a 16-bit address is to be addressed. the nvr and dom spaces are all 8-bit address sections, and for these areas, this bit should be 0?b. note (2): block 256-byte nvr writes will not occur unless the wrtp pin is set low. nvr write page size controls page size for bl ock operations only. note (3): this area corresponds to the xenpak-defined customer area; see xenpak spec r3.0 section 10.12.22. writes will be perfo rmed one byte at a time. note (4): the i 2 c clock speeds listed are approximate. they are derived by divisi on from the cmu, locked to the rfcp/n inputs. at 156.25mhz, th e nominal 100khz clock will actually be 156.25/1.6khz, just over 97.5khz. see also the notes to table 117. note (1): these bits are latched high on any internal error condition detected. they are reset low (cleared) on being read. note (2): these bits are set if the exor sum calculated from t he indicated range is not the same as the value read into the list ed checksum register. note that this is not the same as the xenpak-defined checksum calculation. contac t intersil for a method of rec onciling these two checksum calcul ations. table 19. i 2 c one-byte operation write data register mdio register address = 1.32772 (1.8004?h) bit name setting default r/w description 1.32772.15:8 reserved 00?h ro 1.32772.7:0 write data i 2 c write data 00?h r/w data to be written by 1-byte write operation table 20. nvr i 2 c operation control register mdio register address = 1.32773 (1.8005?h) bit name setting default r/w description 1.32773.15:9 reserved 00?h ro 1.32773.8 long memory (1) 1 =16 bit 0 = 8 bit 0?b r/w length of address for i 2 c device selected 1.32773.7 nvr write size 0?b r/w 1 = block write all 256 bytes to nvr (2) 0 = write only 1.807f:ae?h to nvr (3) 1.32773.6:4 i 2 c bus speed speed of i 2 c scl clock (4) (derived from ref_clock) 100?b r/w 111 = 400khz 110 = 200khz 101 = 150khz 100 = 100khz 011 = 40khz 010 = 20khz 001 = 10khz 000 = 4khz 1.32773.3:2 nvr ack error count 11 = 63 10 = 16 01 = 4 00 = 1 11?b r/w number of ack failures at any address before i 2 c operation failure is reported 1.32773.1:0 nvr write page size (2) 11 = 32 bytes 10 = 16 bytes 01 = 8 bytes 00 = 4 byte 01?b r/w the i 2 c interface block write operation will issue a stop and wait for the eeprom every time after this number of bytes are sent out table 21. nvr i 2 c operation status register mdio register address = 1.32774 (1.8006?h) bit name setting default r/w description 1.32774.15 xp_ena xp_ena pin ro 1 = xp_ena pin high, 0 = low 1.32774.14:4 reserved 0000?h ro 1.32774.3 vendor specific area exor sum check error flag 0?b ro lh 1 = 1.8106 ! = exor ( 1.80ae:8105) 0 = 1.8106 = exor ( 1.80ae:8105) (2) 1.32774.2 customer write area exor sum check error flag 0?b ro lh 1 = 1.80ad ! = exor ( 1.807e:80ac) 0 = 1.80ad = exor ( 1.807e:80ac) (2) 1.32774.1 reserved 0?b ro lh (1) 1.32774.0 nvr area exor sum check error flag 0?b ro lh 1 = 1.807d ! = exor ( 1.8007:807c) 0 = 1.807d = exor ( 1.8007:807c) (2) bbt3821
26 note (1): only register values operated on by the bbt3821 are i ndividually listed. the others are merely copied from the i 2 c nvr space. note (2): although data can be written to these registers, it will be volatile, unless the ?write nvr? operation as specified in ?writing eeprom space through the i2c interface? on page 19 is performed. note (3): checksum to be calculated from 1.8007?h to 1.807c?h. host can check for validity. note (4): if wrtp pin is high, this is the only area that can be written by the user. see also note (2) above. note (5): checksum to be calculated from 1.807e?h to 1.80ac?h. note (6): checksum to be calculated from 1.80ae?h to 1.8105?h. note (1): suggested values are given, for a full lx4 module with four individual-lane dom circuits, at least one having the dom data at device address a2?h. note (2): last three significant bits of the (default) dom i 2 c device address (nb lsb is a read/write flag). upper bits are assumed to be ?1010?b, device address will be (a0?h + 2*(<1.32890.2:0>). a device must be present at this address for correct operation if bit 6 is set. note (3): although data can be written to this register, it shoul d only be done for writing the nvr, using the ?write nvr? opera tion as specified in ?writing eeprom space through the i2c interface? on page 19. the values here should normally only be loaded from the nvr, since they could affect the operation of the bbt3821 if incorrect. table 22. xenpak nvr register copy mdio xenpak/xpak/x2 nvr register addresses = 1.32775:33030 (1.8007:8106?h) byte address name description (1) suggested value r/w details dec hex 1.32775 to 1.32817 1.8007 to 1.8031 nvr register copy xenpak nvr register copies r/w (2) 1.32818 to 1.32821 1.8032 to 1.8035 pkg oui xenpak/xpak/x2 package oui (bits 3 to 24) xenpak = 0008be xpak = 000acb x2 = 000c64 r/w (2) mirrored to 1.14:15 (1.e:f?h) 1.32822 to 1.32889 1.8036 to 1.8079 nvr register copy xenpak nvr register copies r/w (2) 1.32890 1.807a dom ctrl dom capability bits r/w (2) table 23 1.32891 1.32892 1.807b 1.807c nvr reg copy xenpak nvr register copies r/w (2) 1.32893 1.807d basic chksm ba sic field checksum (3) ( 1.8007:807c) 1.32894 to 1.32940 1.807e to 1.80ac nvr register copy customer writable area (4) r/w (2) 1.32941 1.80ad cstm chksm customer area checksum (5) ( 1.807e:80ac) 1.32942 to 1.33027 1.80ae to 1.8103 nvr register copy vendor specific area r/w (2) 1.33028 1.8104 a/c size auto-configure size ( n ) see page 16 (or 00 or ff?h) see table 92 1.33029 1.8105 a/c pointer auto-configure pointer ( s ) 1.33030 1.8106 vndr chksm vendor specific checksum (6) ( 1.80ae:8105) table 23. xenpak digital optical monitoring (dom) capability register mdio (xenpak) register, address = 1. 32890 (1. 807a?h) bit name setting suggested value (1) r/w (3) description 1.32890.15:8 reserved 000?h 1.32890.7 dom ctrl reg 1 = implemented 0 = not implemented 1?b r/w dom control/status register 1.a100?h 1.32890.6 dom system 1?b r/w dom implemented 1.32890.5 lane-by lane 1?b r/w wdm lane-by-lane dom; registers 1.a0c0:a0ff?h valid 1.32890.4 lbc scale 1 = 10 a 0 = 2 a r/w laser bias scale factor 1.32890.3 reserved 1.32890.2:0 dom address 001?b r/w i 2 c device address of (initial) dom ic (2) bbt3821
27 xenpak lasi and dom registers (1.9000? h to 1.9007?h & 1.a000?h to 1.a100?h) note (1): where two values are given, default depends on lx4/cx4 select lx4_mode pin. first value is lx4 value. the value may be overwritten by the auto- configure operation (see ?auto-configuring control registers? on page 16 and table 92 for details). note (1): where two values are given, default depends on lx4/cx4 select lx4_mode pin. first value is lx4 value. the value may be overwritten by the auto- configure operation (see ?auto-configuring control registers? on page 16 and table 92 for details). note (1): the default values may be overwritten by the auto-configure operation (see ?auto-configuring control registers? on pag e 16 and table 92 for details). since on power up or reset several lasi contributors will initially be in the ?fault? condition (in particular, byte synch and lane a lignment, and their derivatives), it may be advisable for a host to clear these before enabling these to trigger lasi. note (2): see description of the general purpose input/output (gpio) pins and bits for a description of how they contribute to t he lasi system. table 24. xenpak lasi rx_alarm control register mdio register, address = 1.36864 (1.9000?h) bit name setting default (1) r/w description 1.36864.15:7 reserved 000?h 1.36864.6 pcs byte s 1 = trigger lasi by corresponding bit of 1.36867 (1.9003?h) 0 = lasi ignores corresponding bit of 1.36867 (1.9003?h) 0?b r/w pcs byte sync fail lasi enable 1.36864.5 rx power 1?b r/w receive laser pwr/sig det lasi enable 1.36864.4 pma lf 1?b r/w pma rx local fault lasi enable 1.36864.3 pcs lf 1?b r/w pcs rx local fault lasi enable 1.36864.2 pcs code 0?b/1?b r/w 8b/10b code violation lasi enable 1.36864.1 dom rx 1?b r/w dom rx or rx efifo fault lasi enable 1.36864.0 phy rx lf 1?b r/w phy rx local fault lasi enable table 25. xenpak lasi tx_alarm control register mdio register, address = 1.36865 (1.9001?h) bit name setting default (1) r/w description 1.36865.15:11 reserved 000?h 1.36865.10 phy s_d 1 = trigger lasi from corresponding bit of 1.36868 (1.9004?h) 0 = lasi ignores corresponding bit of 1.36868 (1.9004?h) 0?b/1?b r/w phy xs signal detect lasi enable 1.36865.9 lbc 1?b/0?b r/w laser bias current fault lasi enable 1.36865.8 ltemp 1?b/0?b r/w laser te mperature fault lasi enable 1.36865.7 lop 1?b/0?b r/w laser output power fault lasi enable 1.36865.6 tx lf 1?b/0?b r/w transmit local fault lasi enable 1.36865.5 byte sync 0?b/1?b r/w phy xs byte sync fail lasi enable 1.36865.4 pma lf 1?b r/w pma tx local fault lasi enable 1.36865.3 pcs lf 1?b/0?b r/w pcs tx local fault lasi enable 1.36865.2 tx efifo 0?b/1?b r/w transmit efifo error lasi enable 1.36865.1 dom tx/ phy code 1?b r/w dom tx or phy xs 8b/10b code violation fault lasi enable 1.36865.0 phy tx lf 1?b r/w phy tx local fault lasi enable table 26. xenpak lasi control register mdio register, address = 1.36866 (1.9002?h) bit name setting default (1) r/w description 1.36866.15:4 reserved 000?h 1.36866.3 gpio 1 = trigger lasi via bit in 1.36869 (1.9005?h) 0 = lasi ignores bit 0?b r/w enable gpio pins to trigger lasi (2) 1.36866.2 rx_alarm 0?b r/w enable rx_alarm to trigger lasi 1.36866.1 tx_alarm 0?b r/w enable tx_alarm to trigger lasi 1.36866.0 ls_alarm 0?b r/w enable link status change to trigger lasi bbt3821
28 note (1): where two descriptions are given, depends on lx 4/cx4 select lx4_mode pin. first value is lx4 value note (2): these mirrored bits will be cleared on a read of either this register or of their respective mirroring registers. note (3): this bit is derived from the or of the los bits (1.c00a. 3:0). in the case of a signal which is close to the los thresh old value, so that los is changing over time for one or more lanes, this bit may give a ?fail? indica tion even though the signal_detect function declares the signal ?g ood?, and byte synch and lane align all indicate a ?good? signal. note (1): where two descriptions are given, depends on lx 4/cx4 select lx4_mode pin. first value is lx4 value note (2): these mirrored bits will be cleared on read of either this register or their respective registers. table 27. xenpak lasi rx_alarm status register mdio register, address = 1.36867 (1.9003?h) bit name setting default r/w description (1) 1.36867.15:6 reserved 000?h 1.36867.6 pcs byte synch 1 = alarm condition is detected 0 = no alarm condition is detected 0?b ro/lh pcs byte sync fail (l ogical nand of bits 3.24.[3:0]) 1.36867.5 rx receive power/level 0?b ro/lh lx4: receive laser power from oprxop pin (for polarity see 1.49181) cx4: loss of signal detect (3) 1.36867.4 pma lf 0?b ro/lh pma/pmd rx local fault: mirror to bit 1.8.10 (2) 1.36867.3 pcs lf 0?b ro/lh pcs rx local fault: mirror to bit 3.8.10 (2) 1.36867.2 pcs code 0?b ro/lh pcs 8b/10b code violation in any lane of pcs 1.36867.1 dom rxflg/ rx efifo 0?b ro/lh lx4: dom rx_flag (from polling) cx4: rx efifo over/underflow fault 1.36867.0 phy rx lf 0?b ro/lh phy rx local fault status: mirror to bit 4.8.10 (2) table 28. xenpak lasi tx_alarm status register mdio register, address = 1.36868 (1.9004?h) bit name setting default r/w description (1) 1.36868.15:11 reserved 000?h 1.36868.10 phy s_d 1 = alarm condition is detected 0 = no alarm condition is detected 0?b ro/ lh lx4: no fail detected cx4: phy xs signal detect fail (xaui) 1.36868.9 lbc 0?b ro lh lx4: laser bias current fault (from optxlbc pin, for polarity see 1.49181) cx4: no failure detectable 1.36868.8 ltemp 0?b ro lh lx4: laser temperature fault (from opttemp pin, for polarity see 1.49181) cx4: no failure detectable 1.36868.7 lop 0?b ro lh lx4: laser output power fault (from optxlop pin, for polarity see 1.49181) cx4: no failure detectable 1.36868.6 tx lf 0?b ro lh transmit local faul t (from tx_fault pin, for polarity see 1.49170) 1.36868.5 byte sync 0?b ro lh lx4: no fail detected cx4: phy xs byte sync fail status 1.36868.4 pma lf 0?b ro lh pma tx local f ault status: mirror to bit 1.8.11 (2) 1.36868.3 pcs lf 0?b ro lh lx4: pcs tx local fault status: mirror to bit 3.8.11 (2) cx4: no failure detectable 1.36868.2 tx efifo 0?b ro lh lx4: no fail detected cx4: transmit efifo error status 1.36868.1 dom tx/ phy code 0?b ro lh lx4: dom tx_flag (from polling) cx4: phy xs 8b/10b code violation 1.36868.0 phy tx lf 0?b ro lh phy tx local fault status: mirror to bit 4.8.11 (2) bbt3821
29 note (1): this bit is latched high on any change in the co ndition detected. it is reset low (cleared) on being read. note (1): these bits control (select) alarm signals (bits) in r egister 1.41072 (1.a070?h) to generate the tx_flag bit of registe r 1.36868 (1.9004?h) to trigger tx_alarm and hence lasi. note (2): the default values may be overwritten by the auto-configure operation (see ?auto-configuring control registers? on pag e 16 and table 92 for details). note (1): these bits control (select) alarm signals (bits) in register 1.41073 (1.a071?h) to generate the rx_flag bit of registe r 1.36867 (1.9003?h) to trigger rx_alarm and hence lasi. note (2): the default value may be overwritten by the auto-configure operation (see ?auto-configuring control registers? on page 16 and table 92 for details). table 29. xenpak lasi status register mdio register, address = 1.36869 (1.9005?h) bit name setting default r/w description 1.36869.15:4 reserved 000?h 1.36869.3 gpio alarm 1 = alarm condition is detected 0 = no alarm condition is detected 0?b ro logic or of signals in register 1.49169.[15:8] (1.c011h), which come from gpio pins. 1.36869.2 rx_alarm 0?b ro logic or of signals in register 1.36867 rx_alarm status register 1.36869.1 tx_alarm 0?b ro logic or of signals in register 1.36868 tx_alarm status register 1.36869.0 ls_alarm 0?b ro lh (1) link status logic change in and of ?pmd signal ok? (1.10.0), ?pcs lane alignment? (3.24.12), and ?phy xs lane alignment? (4.24.12) table 30. xenpak dom tx_flag control register mdio register, address = 1.36870 (1.9006?h) bit (1) name setting default (2) r/w description 1.36870.15:8 reserved 000?h 1.36870.7 ttmp_hi 1 = enable alarm 0 = disable alarm 0?b r/w transceiver temp high alarm enable 1.36870.6 ttmp_lo 0?b r/w transceiver temp low alarm enable 1.36870.5:4 reserved 0?h r/w 1.36870.3 lbc_hi 1 = enable alarm 0 = disable alarm 0?b r/w laser bias current high alarmenable 1.36870.2 lbc_lo 0?b r/w laser bias current low alarm enable 1.36870.1 lop_hi 0?b r/w laser output power high alarm enable 1.36870.0 lop_lo 0?b r/w laser output power low alarm enable table 31. xenpak dom rx_flag control register mdio register, address = 1.36871 (1.9007?h) bit (1) name setting default (2) r/w description 1.36871.15:8 reserved 000?h 1.36871.7 rop_hi 1 = enable alarm 0 = disable alarm 0?b r/w receive optical power high alarm enable 1.36871.6 rop_lo 0?b r/w receive optical power low alarm enable 1.36871.5:0 reserved 00?h bbt3821
30 note (1): these1-byte register values are merely copied by the bbt3821 from the i 2 c address space on power-up or reset, or on a periodic direct dom update operation (i.e. with register bit 1.c018?h.2 table 51 not set) under the control of register 1.a100?h (table 38). for further de tails see table 27 in the xenpak msa rev 3.0 specification, especially note 2. if it is desired to write this data into a dom device through the mdio interface, it will need to be written one byte at a time via the methods discussed in ?mdio register addressing? on page 15. table 32. xenpak dom alarm & warning threshold registers copy xenpak/xpak/x2 dom registers = 1.40960:40999 & 41032:41055 (1.a000:a027?h & a048:a05f?h) (1) byte address memory address description default r/w details dec hex 1.40960 to 1.40967 1.a000 to 1.a007 00 to 07 transceiver temp high & low alarm & warning thresholds ro byte order: high alarm msb:lsb low alarm msb:lsb high warning msb:lsb low warning msb:lsb 1.40968 to 1.40975 1.a008 to 1.a00f 08 to15 reserved ro 1.40976 to 1.40983 1.a010 to 1.a017 16 to 23 laser bias current high & low alarm & warning thresholds (lane 0 or common to all lanes) ro 1.40984 to 1.40991 1.a018 to 1.a01f 24 to 31 laser output power high & low alarm & warning thresholds ro 1.40992to 1.40099 1.a020 to 1.a027 32-39 receive optical power high & low alarm & warning thresholds ro 1.41032 to 1.41055 1.a048 to 1.a05f 72 to 95 lane-by-lane laser bias current high & low alarm & warning thresholds (or zero) ro order: lane 1 to lane 3 table 33. xenpak dom monitored a/d values register copy mdio xenpak/xpak/x2 dom register addresses = 1.41056:41069 & 1.41152:41215 (1.a060:a06d?h & 1.a0c0:a0ff) byte address memory address description (1) default r/w details dec hex 1.41056 1.41057 1.a060 1.a061 96 & 97 ?farthest out of range/representative? transceiver temperature (2) ro msb:lsb 1.41058 1.41059 1.a062 1.a063 98 & 99 reserved 1.41060 1.41061 1.a064 1.a065 100 & 101 ?farthest out of range/representative? laser bias current (2) ro msb:lsb 1.41062 1.41063 1.a066 1.a067 102 & 103 ?farthest out of range/representative? laser output power (2) ro msb:lsb 1.41064 1.41065 1.a068 1.a069 104 & 105 ?farthest out of range/representative? receive optical power (2) ro msb:lsb 1.41066 - 1.41069 1.a06a to 1.406d 106 to 109 reserved 1.41070 to 1.41077 1.a06e to 1.a075 110 to 117 dom status, capability, and alarm flags (2) . see table 34 to table 37 ro 1.41078 to 1.41151 1.a076 to 1.a0bf 118 to 191 reserved 1.41152:3 1.a0c0:1 192:193 lane 0 transceiver temperature (3) ro msb:lsb 1.41154:5 1.a0c2:3 194:195 reserved ro msb:lsb 1.41156:7 1.a0c4:5 196:197 lane 0 laser bias current (3) ro msb:lsb 1.41158:9 1.a0c6:7 198:199 lane 0 laser output power (3) ro msb:lsb 1.41160:1 1.a0c8:9 200:201 lane 0 receive optical power (3) ro msb:lsb 1.41162:7 1.a0ca:f 202:207 reserved 1.41168:9 1.a0d0:1 208:209 lane 1 transceiver temperature (3) ro msb:lsb bbt3821
31 note (1): these 1-byte register values are merely copied by the bbt3821 from the i 2 c address space on reset (if enabled), on demand, or periodically under the control of register 1.a100?h (table 38). note (2): if the ?indirect dom enable? bit (register bit 1.c018?h.2 table 51) is not set, a four-lane external dom device is exp ected to determine the ?farthest out of range? or ?representative? values for these registers, according to the rules of note 1 to table 28 in the xenpak msa rev 3.0 s pecification. a single one-lane dom device system will provide the values from the single dom devi ce here only. if the ?indirect dom enable? bit is set, ?repre sentative? is defined by register bits 1.c018?h.1:0 (table 51), and the values from the specified lane?s dom are entered here also. note (3): if the ?indirect dom enable? bit (register bit 1.c018?h.2 table 51) is not set, a four-lane external dom device is exp ected to provide the lane-by-lane data. for a single one-lane dom device system these values are 00?h. the lane-by-lane data is obtained from the i 2 c address space via the pointers defined in registers 1.c019:c?h (table 53 & table 54), if the ?indirect dom enable? bit is set (register 1.c018?h table 51). note (1): this 1-byte register value is merely copied by the bbt3821 from the i 2 c address space on power-up or reset, or on a periodic or on-demand direct dom update operation (i.e. with register bit 1.c018?h.2 table 51 not set) under the control of register 1.a100?h (table 38). the bb t3821 takes no action as a result of the values copied. note (2): assumes nvr/dom read succeeds 1.41170:1 1.a0d2:3 210:211 reserved ro msb:lsb 1.41172:3 1.a0d4:5 212:213 lane 1 laser bias current (3) ro msb:lsb 1.41174:5 1.a0d6:7 214:215 lane 1 laser output power (3) ro msb:lsb 1.41176:7 1.a0d8:9 216:217 lane 1 receive optical power (3) ro msb:lsb 1.41178:83 1.a0da:f 218:223 reserved 1.41184:5 1.a0e0:1 224:225 lane 2 transceiver temperature (3) ro msb:lsb 1.41186:7 1.a0e2:3 226:227 reserved ro msb:lsb 1.41188:9 1.a0e4:5 228:229 lane 2 laser bias current (3) ro msb:lsb 1.41190:1 1.a0e6:7 230:231 lane 2 laser output power (3) ro msb:lsb 1.41192:3 1.a0e8:9 232:233 lane 2 receive optical power (3) ro msb:lsb 1.41194:9 1.a0ea:f 234:239 reserved 1.41200:1 1.a0f0:1 240:241 lane 3 transceiver temperature (3) ro msb:lsb 1.41202:3 1.a0f2:3 242:243 reserved ro msb:lsb 1.41204:5 1.a0f4:5 244:245 lane 3 laser bias current (3) ro msb:lsb 1.41206:7 1.a0f6:7 246:247 lane 3 laser output power (3) ro msb:lsb 1.41208:9 1.a0f8:9 228:249 lane 3 receive optical power (3) ro msb:lsb 1.41210:5 1.a0fa:f 250:255 reserved table 33. xenpak dom monitored a/d values register copy (continued) mdio xenpak/xpak/x2 dom register addresses = 1.41056:41069 & 1.41152:41215 (1.a060:a06d?h & 1.a0c0:a0ff) byte address memory address description (1) default r/w details dec hex table 34. xenpak optional dom status bits register mdio register, address = 1.41070 (1.a06e?h) bit name setting default r/w description (1) 1.41070.15:1 reserved 0000?h 1.41070.0 data_ready_bar 1 = not ready 0 = ready 0?b (2) ro high during power-up and first nvr/dom read. after that set low. bbt3821
32 note (1): these 1-byte register values are merely copied by the bbt3821 from the i 2 c address space on power-up or reset, or on a periodic or on-demand direct dom update operation (i.e. with register bit 1.c018?h.2 table 51 not set) under the control of register 1.a100?h (table 38). the bbt3821 takes no action as a result of the values copied. note (1): these 1-byte register values are copied by the bbt3821 from the i 2 c address space on power-up or reset, or on any dom read operation. if the ?indirect dom enable? bit (register bit 1.c018?h.2 table 51) is not set, a fo ur-lane external dom device is expected to determine the val ues for these registers, according to section 11.3 in the xenpak msa rev 3.0 specificati on. a single one-lane dom device system will provide the values from the single dom device here. if the ?indirect dom enable? bit is set, the values from the ?representative? (as set by register bits 1.c018?h.1: 0 in table 51) lane dom are entered here. see ?dom registers? on page 16. these bits are gated with the enable bits in 1.9006:7 (table 30 & table 31) and the lx4/cx4 select lx4_mode pin to drive bits 1.9004.1 & 1.9003.1 (table 28 & table 27), and if enabled via 1.9002 & 1.9001 (table 25 & table 24) to d rive the lasi pin. table 35. xenpak dom extended capability register mdio register, address = 1.41071 (1.a06f?h) bit name setting default r/w description (1) 1.41071.15:8 reserved 00?h (1) 1.41071.7 tt_able 1 = indicates capability implemented 0 = not implemented ro transceiver temp monitoring capable 1.41071.6 lbc_able ro laser bias current monitoring capable 1.41071.5 lop_able ro laser output power monitoring capable 1.41071.4 rop_able ro receive optical power monitoring capable 1.41071.3 al_able ro alarm flags for monitored quantities 1.41071.2 wn_able ro warning flags for monitored quantities 1.41071.1 mon_lasi ro monitoring quantities input to lasi 1.41071.0 reserved ro monitoring capable table 36. xenpak dom alarm flags register mdio register, address = 1.41072:3 (1.a070:1?h) bit name setting default r/w description (1) 1.41072.15:8 reserved 00?h (1) ro 1.41072.7 tt_high 1 = alarm set 0 = alarm not set 0?b ro transceiver temp high alarm 1.41072.6 tt_low 0?b ro transceiver temp low alarm 1.41072.5:4 reserved 00?b 1.41072.3 lbc_high 1 = alarm set 0 = alarm not set 0?b ro laser bias current high alarm 1.41072.2 lbc_low 0?b ro laser bias current low alarm 1.41072.1 lop_high 0?b ro laser output power high alarm 1.41072.0 lop_low 0?b ro laser output power low alarm 1.41073.15:8 reserved 00?h 1.41073.7 rop_high 1 = alarm set 0 = alarm not set 0?b ro receive optical power high alarm 1.41073.6 rop_low 0?b ro receive optical power low alarm 1.41073.5:0 reserved 00?h table 37. xenpak dom warning flags register mdio register, address = 1.41076:7 (1.a074:5?h) bit name setting default r/w description (1) 1.41076.15:8 reserved 00?h (1) 1.41076.7 tt_high 1 = warning set 0 = warn. not set 0?b ro transceiver temp high warning 1.41076.6 tt_low 0?b ro transceiver temp low warning 1.41076.5:4 reserved 00?b bbt3821
33 note (1): these 1-byte register values are merely copied by the bbt3821 from the i 2 c address space on power-up or reset, or on any dom read operation. if the ?indirect dom enable? bit (register bit 1.c018?h.2 table 51) is not set, a fo ur-lane external dom device is expected to determine the val ues for these registers, according section 11.3 in the xenpak msa rev 3.0 spec ification. a single one-lane dom device system will provide the values from the sing le dom device here. if the ?indirect dom enable? bit is set, the values from the ?representat ive? (as defined by register bits 1.c018?h.1:0 in table 51), lane dom are entered here. note (1): user writes to these bits are not valid unless the comma nd status is idle. the command status will not return to idle until being read after command completion (either succeed or failed). note (2): at the end of a hardware resetn or a register 1.0.15 reset operation, if the xp_ena pin is asserted, and the dom contr ol bits are set in 1.32890 (1.807a), the bbt3821 will automatically begin a ?periodic update, fastest rate read? operation. note (3): the rates of the periodic reads are determined by bits 4:3 of register 1.49176 (1.c018?h), see table 51. vendor-specific pma/pmd and gpio registers (1.c001?h to 1.c01d?h) note (1): these values may be overwritten by the auto-configure operation (see ?auto-configuring control registers? on page 16 an d table 92 for details). note (2): internal test purposes only. note (3): default values depend on setting of lx4/cx4 select lx4_mode pin. lx4 value is shown firs t. note (4): optimum value to meet output templates. contact bitblitz for recommended value. 1.41076.3 lbc_high 1 = warning set 0 = warning not set 0?b ro laser bias current high warning 1.41076.2 lbc_low 0?b ro laser bias current low warning 1.41076.1 lop_high 0?b ro laser output power high warning 1.41076.0 lop_low 0?b ro laser output power low warning 1.41077.15:8 reserved 00?h 1.41077.7 rop_high 1 = warning set 0 = warn. not set 0?b ro receive optical power high warning 1.41077.6 rop_low 0?b ro receive optical power low warning 1.41077.5:0 reserved 00?h table 37. xenpak dom warning fl ags register (continued) mdio register, address = 1.41076:7 (1.a074:5?h) bit name setting default r/w description (1) table 38. xenpak dom operation control and status register mdio register, address = 1.41216 (1.a100?h) bit name setting default r/w description 1.41216.15:4 reserved 0000?h 1.41216.3:2 dom command status (1) current status of dom command 00?b ro 11 = command failed 10 = command in progress/queued 01 = command complete w success 00 = idle 1.41216.1:0 dom command type (1) nvr operation to be performed 11?b (2) r/w 00 = single dom read operation 01 = periodic update, slowest rate (3) 10 = periodic update, intermediate rate (3) 11 = periodic update, fastest rate (3) table 39. pma control 2 register mdio register, address = 1.49153 (1.c001?h) bit name setting default r/w description 1.49153.15 pma dc_o_dis 1 = disable, 0 = normal 0?b (1) r/w pma dc offset disable 1.49153.14 test 0 = normal 0?b (2) (1) r/w user must keep at 0. 1.49153.13 amplitude adjust 1,0?h (1) (3) r/w optimizing setting, tbd (4) 1.49153.12:11 reserved 0?h 1.49153.10:8 pma_los_th 0?h = 160mv p-p 1?h = 240mv p-p 2?h = 200mv p-p 3?h = 120mv p-p 4?h = 80mv p-p else = 160mv p-p lx4: (3) 0?h, cx4: 03?h (1) r/w set the threshold voltage for the loss of signal (los) detection circuit in pma/pmd. nominal levels are listed for each control value. note that the differential peak-to-peak value is twice that listed. 1.49153.7:0 reserved 00?h bbt3821
34 note (1): loopback is from serial i/p to serial o/p. recommende d use for test purposes only; the lanes are swapped, and no pre-e mphasis is performed. note (2): these values may be overwritten by the auto-configure operation (see ?auto-configuring control registers? on page 16 an d table 92 for details). note (1): default values depend on setting of lx4/cx4 select lx4_mode pin. lx4 value is shown firs t. the values may be overwritten by the auto-configure operation (see ?auto-configuring control registers? on page 16 and table 92 for details). note (1): see figure 3 for illustration of the pre-emphasized waveform and meaning of symbols. note (2): this equation is the one used by the ieee 802.3 cx4 working group when discussing pre-emphasis (alias transmit equaliz ation). the template normalization factor of 0.69 in step 6) of ieee 802.3akd5.3 section 54.6.3. 6 reflects 0.31 (31%) pre-emphasis according to this equation. note (3): this is the default value set on power-up or reset if the lx4/cx4 lx4_mode pin is set for cx4 operation. this setting allows for a small loss in the pcb traces and connectors before the ieee 802.3akd5.3 defined tp2 compliance measurement point. the value may be overwritten by the auto-configure operation (see ?auto-configuring control registers? on page 16 and table 92 for details). table 40. pma serial loop back control register mdio register address = 1.49156 (1.c004?h) bit name setting default r/w description 1.49156.15:13 reserved 1.49156.12 pma test lp 1 = enable 0 = disable 0?h (1) r/w serial network test loopback 1.49156.11 pma slp_3 0?b (2) r/w pma serial loop back enable for each individual lane. when high, it routes the internal pma serial output to the pma serial input. 1.49156.10 pma slp_2 0?b (2) 1.49156.9 pma slp_1 0?b (2) 1.49156.8 pma slp_0 0?b (2) 1.49156.7:0 reserved table 41. pma pre-emphasis control mdio register address = 1.49157 (1.c005?h) bit name setting default (1) r/w description 1.49157.15:12 pre_emp lane 3 see table 42 for settings 00?h/07?h r/w configure the level of pma pre-emphasis 1.49157.11:8 pre_emp lane 2 00?h/07?h r/w 1.49157.7:4 pre_emp lane 1 00?h/07?h r/w 1.49157.3:0 pre_emp lane 0 00?h/07?h r/w table 42. pma pre-emphasis control settings (1) address 1.c005?h bits 3:0 pre-emphasis (802.3ak) (2) = (1-v low /v hi ) pre-emphasis value = (v hi / v low )-1 address 1.c005?h bits 3:0 pre-emphasis (802.3ak) (2) = (1-v low /v hi ) pre-emphasis value = (v hi / v low )-1 0000 0% 0 1000 33.0% 0.493 0001 5.0% 0.053 1001 36.5% 0.575 0010 9.5% 0.105 1010 40.0% 0.667 0011 14.0% 0.163 1011 43.0% 0.754 0100 18.5% 0.227 1100 46.0% 0.852 0101 22.0% 0.282 1101 49.0% 0.961 0110 26.5% 0.361 1110 52.0% 1.083 0111 (3) 30.0% 0.429 1111 54.5% 1.198 bbt3821
35 note (1): default values depend on setting of lx4/cx4 select lx4_mode pin. lx4 value is shown first. the value may be overwritte n by the auto-configure operation (see ?auto-configuring control registers? on page 16 and table 92 for details). note (1): these bits are latched low on any sig_det failure condition detected. they are reset high on being read. note (2): these bits are latched high on any los condition detected. they are reset low on being read. note (1): default values depend on setting of lx4/cx4 select lx4_mode pin. lx4 value is shown first. the value may be overwritte n by the auto-configure operation (see ?auto-configuring control registers? on page 16 and table 92 for details). note (1): this reset will not cause a reload of the nvr or dom areas, nor an auto-conf igure operation. it will reset the byte sy nc engine, the lane alignment engine, the fifo pointers, and the i 2 c controller. the bbt3821 will (if ?normally? configured) transmit ||lf|| local fault signals until byte sync and lane alignmen t are re-established, and any dom update in progress may be aborted. table 43. pma/pmd equalization control mdio register address = 1.49158 (1.c006?h) bit name setting default (1) r/w description 1.49158.15:14 reserved 1.49158.3:0 pma eq_coeff 0?h = no boost in equalizer. f?h = boost is maximum 0?h/c?h r/w configuration of the pma/pmd equalizer table 44. pma sig_det and los detector status register mdio register address = 1.49162 (1.c00a?h) bit name setting default r/w description 1.49162.15:8 reserved 00?b 1.49162.7 sig_det_3 1 = cx4 signal detect asserted 0 = cx4 signal detect deasserted 1?b ro/ll (1) signal detect for pma lane 3 1.49162.6 sig_det_2 1?b signal detect for pma lane 2 1.49162.5 sig_det_1 1?b signal detect for pma lane 1 1.49162.4 sig_det_0 1?b signal detect for pma lane 0 1.49162.3 pma_los_3 1 = signal less than threshold 0 = signal greater than threshold 0?b ro/lh (2) loss of signal for pma lane 3 1.49162.2 pma_los_2 0?b loss of signal for pma lane 2 1.49162.1 pma_los_1 0?b loss of signal for pma lane 1 1.49162.0 pma_los_0 0?b loss of signal for pma lane 0 table 45. pma/pmd miscellaneous adjustment register mdio register address = 1.49163 (1.c00b?h) bit name setting default r/w description 1.49163.15:10 reserved 00?h 1.49163.9:6 amplitude output control (1) lx4: 5?h cx4: 3?h r/w 1.49163.5:2 pre-emphasis fine control per lane (1) lx4: 0?h cx4: f?h r/w bit 5 is for lane 3, etc. 1.49163.1:0 reserved internal 00?b r/w test function, do not alter. table 46. pma/pmd/pcs/phy xs soft reset register mdio register address = [1,3:4].49167 ([1,3:4].c00f?h) bit name setting default r/w description 1.49167.15 [3,4].49167.15 soft_reset write 1 to initiate. 0?b r/w sc reset the entire chip except mdio register settings (1) [1,3:4].49167.14:0 reserved bbt3821
36 note (1): the value may be overwritten by the auto-configure operation (see ?auto-configuring control registers? on page 16 and t able 92 for details). note (1): if any of these bits is set to ?1?, it triggers lasi if the corresponding bit in 1.49170.5:0 and the gpio enable bit 1 .36866.3 are set high. note (1): if any of these bits is set to ?1?, it triggers lasi if the corresponding bit in 1.49169.12:8 and the gpio enable bit 1.36866.3 are set high. the polarity that will trigger lasi is set by bits 1.49170.12:8 above. note (2): these values may be overwritten by the auto-configure operation (see ?auto-configuring control registers? on page 16 an d table 92 for details). note (1): the value may be overwritten by the auto-configure operation (see ?auto-configuring control registers? on page 16 and t able 92 for details). table 47. gpio pin direction configure register mdio register address = 1.49168 (1.c010?h) bit name setting default r/w description 1.49168.15:5 reserved 1.49168.4:0 gpio pins configuration 1 = output 0 = input 00?h (1) r/w controls whether gpio pin is used as input or output table 48. gpio pin input status register mdio register address = 1.49169 (1.c011?h) bit name setting r/w description 1.49169.15:13 reserved 1.49169.12:8 lasi i/p value 1 = can trigger lasi (1) 0 = cannot trigger lasi ro/lh xor of gpio pin i/p and invert register 1.49170.13:8. 1.49169.7:5 reserved 1.49169.4:0 gpio pin i/p value 1 = pin hi 0 = pin lo ro original values from gpio pins directly. table 49. tx_fault & gpio pin to lasi configure register mdio register address = 1.49170 (1.c012?h) bit name setting default r/w description 1.49170.15:14 reserved 1.49170.13 invert tx_fault 1 = pin low, 0 = pin high to trigger lasi 0?b (2) r/w control polarity of tx_fault pin which will trigger lasi (if enabled) 1.49170.12:8 invert lasi i/p 1 = invert to lasi 0 = straight to lasi 00?h (2) r/w control xor of gpio pin i/p to lasi i/p register 1.49169.13:8. 1.49170.7:5 reserved 1.49170.4:0 enable lasi i/p 1 = enable (1) 0 = do not enable 00?h (2) r/w enable the gpio pin value to trigger gpio_alarm to lasi table 50. gpio pin output register mdio register address = 1.49171 (1.c013?h) bit name setting default r/w description 1.49171.15:5 reserved 1.49171.4:0 gpio pin output 0 = low 1 = high 00?h (1) r/w controls gpio pin level if set as output bbt3821
37 note (1): the values may be overwritten by the auto-configure operation (see ?auto-configuring control registers? on page 16 and table 92 for details). note (2): if ?indirect dom enable? is set, then the dom a/d and flag values are loaded from the i 2 c spaces pointed to by the indirect mode values in table 53 and table 54, and ?representative? controls which lane?s a/d valu es will appear in 1.a060:d?h. if not, then ?representative? has no effect, and the full dom area is updated from a single dom device. see ?dom registers? on page 16 for details. note (1): see table 38 and table 51 for these registers. note (2): these are the default values. the value in 1.c018?h may be overwritten by the auto-configure operation note (1): the values may be overwritten by the auto-configure operation (see ?auto-configuring control registers? on page 16 and table 92 for details). note (1): the values may be overwritten by the auto-configure operation (see ?auto-configuring control registers? on page 16 and table 92 for details). table 51. dom control register mdio register address = 1.49176 (1.c018?h) bit name setting default (1) r/w description 1.49176.15:6 reserved 1.49176.5 test control 0?b r/w user must keep at 0. 1.49176.4:3 dom update period see table 52 00?h r/w c ontrols rates at which dom a/d values are updated 1.49176.2 indirect dom enable 1 = enable 0 = disable 0?b (2) r/w enable updates from four dom devices. see table 33, table 38 1.49176.1:0 representative lane value 00?b (2) r/w select lane for 1.a060:d?h table 52. dom periodic update waiting time values (approximate, based on ref_clock = 156.25 mhz; default underlined) 1.41216.1:0 (1.a100?h.1:0) bits (1) 1.49176.4:3 (1.c018?h) bits (1) 00 (2) 01 10 11 00 n/a n/a n/a n/a 01 800ms 1000ms 1300ms 1600ms 10 400ms 500ms 600ms 700ms 11 (2) 100 ms (2) 150ms 200ms 300ms table 53. dom indirect mode start address registers mdio register addresses = 1.49177:8 (1.c019:1a?h) bit name setting default (1) r/w description 1.49177.15:8 lane 3 dom start address 60?h r/w start address to read a/d values from dom monitor device of respective lane 1.49177.7:0 lane 2 dom start address 60?h r/w 1.49178.15:8 lane 1 dom start address 60?h r/w 1.49178.7:0 lane 0 dom start address 60?h r/w table 54. dom indirect mode device address registers mdio register addresses = 1.49179:80 (1.c01b:1c?h) bit name setting default (1) r/w description 1.49179.15:9 lane 3 dom device address 54?h r/w note: i 2 c device address to read a/d values from dom monitor device of respective lane is twice set value. thus ?default? column addresses are a8?h, a6?h a4?h and a2?h for lanes 3, 2, 1 & 0 respectively. lsb reflects ?read? operation value 1.49179.8 not used, set by current operation 1.49179.7:1 lane 2 dom device address 53?h r/w 1.49179.0 not used, set by current operation 1.49180.15:8 lane 1 dom device address 52?h r/w 1.49180.7 not used, set by current operation 1.49180.7:1 lane 0 dom device address 51?h r/w 1.49180.0 not used, set by current operation bbt3821
38 note (1): the values may be overwritten by the auto-configure operation (see ?auto-configuring control registers? on page 16 and table 92 for details). note (1): ?v? is a version number. see ?jtag & ac-jtag o perations? on page 53 for a note about the version number. note (2): for rows with ?a?, the default value may be overwritten by the auto-configure operation (see ?auto-configuring control registers? on page 16 and table 92 for details). note (3): read value depends on status signal values. value shown indicates ?normal? operation. note (4): the ieee 802.3ae specification allows this to be all ze roes. a xenpak (etc.) host can more readily determine where the nvr registers are if this value is zero. note (5): if ieee 802.3ae (and default) setting for pcs loopback, 180f?h. if pcs loopback allowed, 1c0f?h. see table 61 and table 64. table 55. optical status & control pin polarity register mdio register address = 1.49181 (1.c01d?h) bit name setting default (1) r/w description 1.49181.15:7 reserved 1.49181.6 oprlos[3:0] 1 = low -> los 0 = high -> los 0?b r/w input polarity to 1.10 and enable byte synch in lx4 mode 1.49181.5 tx_ena[3:0] 1 = active low 0 = active hi 0?b r/w polarity of tx_ena outputs 1.49181.4 tx_enc 0?b r/w polarity of tx_enc input 1.49181.3 oprxop 1 = pin low to trigger lasi 0 = pin high to trigger lasi 0?b r/w control polarity of re spective input pins which will trigger lasi (if enabled) 1.49181.2 opttemp 0?b r/w 1.49181.1 optxlbc 0?b r/w 1.49181.0 optxlop 0?b r/w table 56. mdio pcs devad 3 registers pcs device 3 mdio registers address name description default ac (2) r/w details dec hex 3.0 3.0 pcs control 1 reset, enabl e loop back mode. 2040?h r/w table 57 3.1 3.1 pcs status 1 pcs fault, link status 0004?h (3) ro ll table 58 3.2:3 3.2:3 id code manufacturer and device oui 01839c6v?h ro see (1) 3.4 3.4 speed ability 10gbps ability 0001?h ro table 7 3.5 3.5 ieee devices devices in pa ckage, clause 22 capable 001a?h ro table 8 3.6 3.6 vendor devices vendor specific devices in pkg 0000?h ro table 8 3.7 3.7 pcs type ieee pcs type select register 0001?h ro table 59 3.8 3.8 pcs status 2 device present, local fault, type summary 8002?h (3) ro table 60 3.14:15 3.e:f package id package oui, etc. 00000000?h ro see (4) 3.24 3.18 pcs-x status 3 ieee 10gbase-x pcs status register see (5) ro table 61 3.25 3.19 pcs test ieee 10gb ase-x pcs test control register 0000?h r/w table 62 3.49152 3.c000 pcs control 2 pcs control register 2 0f6f?h a r/w table 63 3.49153 3.c001 pcs control 3 pcs control register 3 0801?h a r/w table 64 3.49154 3.c002 pcs error pcs internal error code register 00fe?h a r/w table 66 3.49155 3.c003 pcs idle pcs internal idle code register 0007?h a r/w table 67 3.49156 3.c004 pcs // loop back pcs parallel network loop back control register 0000?h a r/w table 68 3.49159 3.c007 test_flags receive path test & status flags 0000?h ro lh table 69 3.49160 3.c008 output ctrl output control and test function aaaa?h r/w table 70 3.49161 3.c009 half rate half rate clock mode enable 0000?h r/w table 71 3.49164 3.c00c bist ctrl bist control register 0000?h r/w table 72 3.49165 3.49166 3.c00d 3.c00e bist error bist error counter registers 0000?h ro/ rcnr ta b l e 7 3 3.49167 3.c00f soft reset reset (non mdio) 0000?h r/w sc table 46 bbt3821
39 ieee pcs registers (3.0 to 3.25/3.0019?h) note (1): this bit is not permitted to be a pcs loopback bit by ieee 802.3ae-2002 subclause 45.2.3.1.2 in 10gbase-x pcs devices. intersil has submitted a maintenance request (#1113) to allow that use of this bit. many xenpak hosts, however, expect this loopback (which is mandatory for 10gbase-r pcs devices). setting the 3.c001?h.7 bit, (table 64) will activate this loopback enable bit, but c ause the bbt3821 to be non-confor ming to the current 802.3 specification. see ?loopback modes ? on page 13). note (1): this bit is latched low on a detected fa ult condition. it is set high on being read. note (1): although the 802.3ae specification describes this register as type r/w, this register cannot have any value other than that reflecting the 10gbase-x pcs. thus writing any other value is ignored, and the register is in effect type ro. table 57. ieee pcs control 1 register mdio register address = 3.0 (3.0000?h) bit(s) name setting default r/w description 3.0.15 1.0.15 4.0.15 reset 1 = reset 0 = reset done, normal operation 0?b r/w sc writing 1 to this bit will reset the whole chip, including the mdio registers. 3.0.14 (1) pcs_lb_en optionally, enable pcs loopback, otherwise reserved 0?b r/w if enabled by en_pcs_lb (see bit 3.c001?h.7, table 64) perform pcs loopback, and is a r/w bit; otherwise, effectively a reserved ro 0?b bit (1) . 3.0.13 speed select 1 = 10gbps 1?b ro 1 = bits 5:2 select speed 3.0.12 reserved 00?h 3.0.11 lopower 0 = normal power 0?b r/w no low power mode, writes ignored 3.0.10:7 reserved 3.0.6 speed select 1 = 10gbps 1?b ro 1 = bits 5:2 select speed 3.0.5:2 speed select 0000 = 10gbps 0?h ro operates at 10gbps 3.0.1:0 reserved 0?b table 58. ieee pcs status 1 register mdio register address = 3.1 (3.0001?h) bit name setting default r/w description 3.1.15:8 reserved 00?h 3.1.7 local fault 1 = pcs local faul t 0 ro derived from register 3.0008?h 3.1.6:3 reserved 0?h 3.1.2 rx link up 1 = pcs rx link up 0 = pcs rx link down 1 (1) ro ll (1) ?up? means cx4/lx4 signal level is ok, byte synch and lane-lane alignment have all occurred 3.1.1 lopwrable low power ability 0 ro device does not support a low power mode 3.1.0 reserved 0 table 59. ieee pcs type select register mdio register address = 3.7 (3.0007?h) bit name setting default r/w description 3.7.15:2 reserved 000?h 3.7.1:0 pcs type 01 = 10gbase-x 01b ro (1) writes ignored bbt3821
40 note (1): these bits are latched high on any fault condition detected. they are reset low (cleared) on being read. they will als o be reset low on reading the lasi registers 1.9003?h (bit 10, see table 27) or 1.9004?h (bit 11, see table 28) note (1): the status of these bits depends on the signal conditi ons. default shown is for normal operation. the bits contribute to the rx local fault bit, see table 60. note (2): see note (1) to table 57, note (2) to table 64 and/or ?pcs (parallel) loopback (4.c004.[3:0] & optionally 3.0.14)? under ?loopback modes ? on page 13. if enabled, this register bit does not conf orm to the ieee 802.3ae-2002 specification. note (1): for other test pattern generation capabilities incorporated in the bbt3821, including cjpat and crpat, see table 72. table 60. ieee pcs status 2 device present & fault summary register mdio register address = 3.8 (3.0008?h) bit name setting default r/w description 3.8.15:14 device present 10 = device present 10?b ro when read as ?10?, it indicates that a device is present at this device address 3.8.13:12 reserved 3.8.11 tx localflt 1 = tx local fault; on egress channel 0?b ro lh (1) pll lock failure is only pcs tx fault 3.8.10 rx localflt 1 = rx local fault; on ingress channel 0?b ro lh (1) lane alignment or byte alignment not done, or loss of signal, from register 3.24 (3.0018?h) 3.8.9:3 reserved 3.8.2 10gbase-w 0 = cannot perform 0?b ro device cannot be 10gbase-w 3.8.1 10gbase-x 1 = can perform 1?b ro device can perform 10gbase-x 3.8.0 10gbase-r 0 = cannot perform 0?b ro device cannot be 10gbase-r table 61. ieee 10gbase-x pcs status register mdio register addresses = 3.24 (3.0018?h) bit name setting default r/w description 3.24.15:13 reserved 3.24.12 lane_align 1 = 4 lanes aligned 0 = lanes not aligned 1?b (1) ro 1 = all four 3g receive lanes (on ingress path) are aligned 3.24.11 test_pattern test pattern abilities 1?b ro 1 = the device is able to generate test patterns for 10gbase-x 3.24.10 pcs loopback ability (2) or reserved 1 = has optional pcs loopback ability. 0?b ro if enabled by en_pcs_lb (see bit 3.c001?h.7, table 64) indicates pcs loopback ability, and is a 1?b bit; otherwise, a reserved 0?b bit (2) . 3.24.9:4 reserved 00?h 3.24.3 lane3 sync 1 = pcs lane is synchronized 0 = pcs lane not synchronized 1?b (1) ro reflects the pcs_sync byte alignment state machine condition; not valid if not enabled in device (see table 63) 3.24.2 lane2 sync 1?b (1) ro 3.24.1 lane1 sync 1?b (1) ro 3.24.0 lane0 sync 1?b (1) ro table 62. ieee 10gbase-x pcs test control register mdio register address = 3.25 (3.0019?h) bit name setting default r/w description 3.25.15:3 reserved 3.25.2 pcs testpaten transmit test pattern enable 0?b r/w 0 = do not transmit test pattern 1 = transmit test pattern 3.25.1:0 pcs testpat type test pattern select 00?b r/w 11 = reserved 10 = mixed frequency test pattern (continuous /k/ = k28.5) 01 = low frequency test pattern (repeat 0000011111 = k28.7) 00 = high frequency test pattern (repeat 0101010101 = d10.2) bbt3821
41 vendor-specific pcs register s (3.c000?h to 3.c00e?h) note (1): the default values may be overwritten by the auto-configure operation (see ?auto-configuring control registers? on pag e 16 and table 92 for details). note (2): these bits are overridden by pcs xaui_en, see table 64 and table 65. note (3): these state machines are implemented according to 802.3ae-2002 clause 48.6.2. note (4): if the rclkmode bits are set to 10?b, the internal xgmii clock from the pcs to the phy xs is set to the recovered cloc k. if the pcs clock psync bit is set (the default), the recovered clock from lane 0 is used for all fo ur lanes, if cleared, or if the rclkmode bits are set to 01?b or 00?b, each lane uses its own recovered clock. if the incoming data is not frequency-synchronous with the local reference clock, data will be corrupted (occa sional characters will be lost, or repeated). table 63. pcs control register 2 mdio register address = 3.49152 (3.c000?h) bit name setting default (1) r/w description 3.49152.15:14 test mode 00?b 00?b r /w user should leave at 00?b 3.49152.13:12 reserved 3.49152.11 pcs clock psync 1?b r/w 1 = synchronize/align four lanes 0 = do not synchronize/align four lanes 3.49152.10 pcs codecena 0 = disable 1 = enable 1?b r/w internal 8b/10b pcs codec enable/disable 3.49152.9:8 pcs cdet[1:0] comma detect select 11?b r/w these bits individual ly enable positive and negative disparity ?comma? detection. 11 = enable both positive and negative comma detection 10 = enable positive comma detection only 01 = enable negative comma detection only 00 = disable comma detection 3.49152.7 pcs dskw_sm_en 0 = disable (2) 1 = enable 0?b r/w enable de-skew state machine control (3) . forced enabled by xaui_en. may not operate correctly unless the pcs_sync_en bit is also set. 3.49152.6:5 pcs rclkmode (4) 11?b = local reference clock 11?b r/w other values should only be used if incoming data is frequency-synchronous with t he local reference clock (4) 3.49152.4 pcs_sync_en 0 = disable (2) 1 = enable 0?b r/w enable 8b/10b pcs coding synchronized state machine (3) to control the byte alignment (ieee ?code-group alignment?) of the high speed de-serializer 3.49152.3 pcs idle_d_en 1 = enabled 0 = disabled 1?b r/w enables idle vs. non- idle detection for lane-lane alignment. overridden by xaui_en, see table 64 3.49152.2 pcs elst_en 1 = enabled 0 = disabled 1?b r/w enable the elastic function of the receiver buffer 3.49152.1 pcs a_align_dis 1 = disabled (1) 0 = enabled 1?b r/w receiver aligns data on in coming ?/a/? characters (k28.3). if disabled (default), receiver aligns data on idle to non- idle transitions (if bit 3 set). overridden by xaui_en, see table 64 3.49152.0 pcs cal_en 1 = enabled 0 = disabled 1?b r/w enable de-skew calculat or of receiver align fifo table 64. pcs control register 3 mdio register address = 3.49153 (3.c001?h) bit name setting default r/w description 3.49153.15:12 reserved 3.49153.11 pcs xaui_en 1 = enable 0 = disable 1?b (1) r/w enables all xaui features per 802.3ae-2002. it is equivalent to setting the configuration bits listed in table 65 (but does not change the actual value of the corresponding mdio registers? bits). 3.49153.10:8 reserved 3.49153.7 en_pcslb_en 0?b (1) enable 3.0.14 loopback control (2) bbt3821
42 note (1): these values may be overwritten by the auto-configure operation (see ?auto-configuring control registers? on page 16 an d table 92 for details). note (2): pcs loopback via bit 3.0.14 (table 57) is not permitted by ieee 802.3ae-2002 for 10gbase-x pcs devices. many xenpak hos ts, however, expect this loopback (which is mandatory for 10gbase-r pcs devices). setti ng this bit will enable this loopback, but cause the bbt3821 to b e non-conforming to the current 802.3 specification. see ?loopback modes ? on page 13). note (3): these bits are overridden by pcs xaui_en, see also table 65. note (4): this state machine is implemented according to ieee 802.3ae-2002 clause 48.2.6. note (1): ?d? is either 3 for pcs or 4 for phy xs. behavior of the two devices is entirely independent of each other. note (1): the value may be overwritten by the auto-configure operation (see ?auto-configuring control registers? on page 16 and t able 92 for details). note (2): these bits are overridden to fe?h by xaui_en, see table 64 and table 65. note (1): the value may be overwritten by the auto-configure operation (see ?auto-configuring control registers? on page 16 and t able 92 for details). 3.49153.6 pcs akr_sm_en 1 = enable random a/k/r 0 = /k/ only (3) 0?b (1) r/w enable pseudo- random a/k/r (4) in inter packet gap (ipg) on pcs transmitter side (vs. /k/ only) 3.49153.5 pcs trans_en 1 = enable 0 = disable (3) overridden by xaui_en, see table 65 0?b (1) r/w this bit enables the transceiver to translate an ?idle? pattern in the internal fifos (matching the value of register 3.c003?h) to and from the xaui idle /k/ comma character or /a/, /k/ & /r/ characters. 3.49153.4 reserved 3.49153.3 tx_sdr pcs receive data rate 0?b (1) r/w 1 = pcs egress takes data from phy xs at half speed 0 = pcs egress takes data from phy xs at full speed 3.49153.2:0 reserved 001?b table 64. pcs control register 3 (continued) mdio register address = 3.49153 (3.c001?h) bit name setting default r/w description table 65. pcs or phy xs xaui_e n control override functions bits overridden by xaui_en bit, d.49153.11 (d.c001?h.11) = 1?b (1) reg. bit (1) name override to default r/w description d.49153.5 trans_en 1 = enable 0?b r/w translates /a/k/r/ to-from /i/ d.49153.6 akr_sm_en 1 = enable 0?b r/w generate pseudo-random /a/k/r/ d.49152.1 a_align_dis 0 = enabled 1?b r/w aligns data on incoming ?||a||? d.49152.4 pcs_sync_en 1 = enable 0?b r/w ieee clause 48.2.6 state machine d.49152.7 dskw_sm_en 1 = enable 0?b r/w ieee clause 48.2.6 state machine d.49154 error code fe?h fe?h r/w internal fifo error character table 66. pcs internal error code register mdio register, address = 3.49154 (3.c002?h) bit name setting default (1) r/w description 3.49154.15:8 reserved 3.49154.7:0 pcs error desired value (2) fe?h r/w error code. these bits allow the internal fifo error control character to be programmed. table 67. pcs internal idle code register mdio register address = 3.49155 (3.c003?h) bit name setting default (1) r/w description 3.49155.15:8 reserved 3.49155.7:0 pcs xg_idle desired value 07?h r/w idle pattern in internal fifos for translation to/from xaui idles bbt3821
43 note (1): the default value may be overwritten by the auto-configure operation (see ?auto-configuring control registers? on page 16 and table 92 for details). note (2): equivalent to a loopback at the xgmii input side of the phy xs. note (1): note (1): these bits are latched high on any fault cond ition detected. they are reset low (cleared) on being read. the y will also be reset low on reading the lasi register 1.9003?h (see table 27) table 68. pcs parallel network loop back control register mdio register address = 3.49156 (3.c004?h) bit name setting default r/w description 3.49156.15:4 reserved 3.49156.3 plp_3 1 = enable pcs parallel network loopback (2) 0 = disable 0?b (1) r/w pcs parallel network loop back enable for each individual lane. when high, routes the cx4/lx4 serial input to the cx4/lx4 serial output via the xgmii side of the pcs. 3.49156.2 plp_2 0?b (1) 3.49156.1 plp_1 0?b (1) 3.49156.0 plp_0 0?b (1) table 69. pcs receive path test and status flags mdio register address = 3.49159 (3.c007?h) bit name setting default r/w description 3.49159.15:12 test flags 0?h rolh special test use only 3.49159.11 efifo_3 1 = efifo error in lane 0 = no efifo error in lane 0?b pcs elasticity fifo overflow/underflow error detection (1) 3.49159.10 efifo_2 0?b rolh 3.49159.9 efifo_1 0?b rolh 3.49159.8 efifo_0 0?b rolh 3.49159.7 code_3 1 = 10b/8b code error in lane 0 = no 10b/8b code error 0?b rolh pcs 10b/8b decoder code violation detection (1) 3.49159.6 code_2 0?b rolh 3.49159.5 code_1 0?b rolh 3.49159.4 code_0 0?b rolh 3.49159.3:0 test flags 0?h rolh special test use only table 70. pma/pcs output control & test function register mdio register address = 3.49160 (3.c008?h) bit name setting default r/w description 3.49160.15:14 reserved 10?b r/w test function, do not alter 3.49160.13 ena_3 enable lane 3 o/p 1?b r/w 0 = disable (indep. of lx4_mode) 3.49160.12:10 reserved 010?b r/w test function, do not alter 3.49160.9 ena_2 enable lane 2 o/p 1?b r/w 0 = disable (indep. of lx4_mode) 3.49160.8:6 reserved 010?b r/w test function, do not alter 3.49160.5 ena_1 enable lane 1 o/p 1?b r/w 0 = disable (indep. of lx4_mode) 3.49160.12:10 reserved 010?b r/w test function, do not alter 3.49160.1 ena_0 enable lane 0 o/p 1?b r/w 0 = disable (indep. of lx4_mode) 3.49160.0 reserved 0?b r/w test function, do not alter bbt3821
44 note (1): see ?bist operation? on page 53 for a description of these tests and patterns. note (2): this short pattern is the first 13458 bytes of the full prbs 2 23 -1 byte pattern, and also has 9 /k/ per lane as ipg note (3): this pattern is an /s/, preamble, the ?short prbs23? pattern, one /t/, and 9 /k/s, repeated. note (4): a soft reset is required to activate the newly selected pattern. note (5): the checker expects at least one /k/ on each lane between pattern repeats table 71. pcs/phy xs half rate clock control register mdio register addresses = 3.49161 & 4.49161 ([3,4].c009?h) bit name setting default r/w description 3.49161.15:4 4.49161.15:4 reserved 0?h r/w 3.49161.3 4.49161.3 half_rate 3 1?b = half rate clock 0?b = full rate clock 0?b r/w lane 3 is running at half rate clock speed 3.49161.2 4.49161.2 half_rate 2 1?b = half rate clock 0?b = full rate clock 0?b r/w lane 2 is running at half rate clock speed 3.49161.1 4.49161.1 half_rate 1 1?b = half rate clock 0?b = full rate clock 0?b r/w lane 1 is running at half rate clock speed 3.49161.0 4.49161.0 half_rate 0 1?b = half rate clock 0?b = full rate clock 0?b r/w lane 0 is running at half rate clock speed table 72. bist control register mdio register address = 3.49164 (3.c00c?h) bit name setting default r/w description (1) 3.49164.15 bist_en bist generator enable 0?b r/w 1 = enable bist generator 0 = disable bist generator 3.49164.14:12 reserved 3.49164.11 bist_dir select bist data output direction 0?b r/w 1 = bist to pcs (transmit path) 0 = bist to xgxs (receive path) 3.49164.10:8 bist_pat select bist generator data pattern (4) 0?h r/w 000 = crpat 001 = cjpat 010 = prbs23 with 9 /k/s as ipg 011 = short prbs23 pattern (2) 100 = jumbo ethernet packet (3) other = reserved 3.49164.7 bist_det bist checker enable 0?b r/w 1 = enable bist checker 0 = disable bist checker 3.49164.6:4 reserved 3.49164.3 bist_src select bist data checker input source 0?b r/w 0 = pcs to bist (receive path) 1 = xgxs to bist (transmit path) 3.49164.2:0 bist_chk select bist checker data pattern (5) 0?h r/w 000 = crpat 001 = cjpat 010 = prbs23 with /k/?s as ipg 011 = short prbs23 pattern (2) 100 = jumbo ethernet packet (3) other = reserved bbt3821
45 note (1): the counters do not rollover at ff?h, and are cleared on read. there is also an error flag bit, see register 4.c007, t able 88. note (1): ?v? is a version number. see ?jtag & ac-jtag o perations? on page 53 for a note about the version number. note (2): for rows with ?a?, the default value may be overwritten by the auto-configure operation (see ?auto-configuring control registers? on page 16 and table 92 for details). note (3): read value depends on status signal values. value shown indicates ?normal? operation. note (4): the ieee 802.3ae spec allows this to be all zeroes. a xenpak (etc.) host can more readily determine where the nvr regi sters are if this value is zero. table 73. bist error counter registers mdio register addresses = 3.49165:6 (3.c00d:e?h) bit name setting default r/w description 3.49165.15:8 bist_err_cnt_3 lane 3 errors 00?h rcnr (1) error byte counter of bist pattern checker on each lane 3.49165.7:0 bist_err_cnt_2 lane 2 errors 00?h rcnr (1) 3.49166.15:8 bist_err_cnt_1 lane 1 errors 00?h rcnr (1) 3.49166.7:0 bist_err_cnt_0 lane 0 errors 00?h rcnr (1) table 74. mdio phy xs devad 4 registers phy xs device 4 mdio registers address name description default ac (2) r/w details dec hex 4.0 4.0 phyxs control 1 reset, enable loop back mode. 2040?h r/w table 75 4.1 4.1 phyxs status 1 pcs fault, link status 0004?h (3) ro (ll) table 76 4.2:3 4.2:3 id code manufacturer and device oui 01839c6v?h ro see (1) 4.4 4.4 speed ability 10gbps ability 0001?h ro table 7 4.5 4.5 ieee devices devices in pa ckage, clause 22 capable 001a?h ro table 8 4.6 4.6 vendor devices vendor specific devices in pkg 0000?h ro table 8 4.8 4.8 phyxs status 2 device present, local fault, type summary 8000?h (3) ro table 77 4.14:15 4.e:f package id package oui, etc. 00000000?h ro see (4) 4.24 4.18 phyxs status 3 10gbase-x phy xgxs status 1c0f?h ro table 78 4.25 4.19 phyxs test 10gbase phy xs test control 0000?h r/w table 79 4.49152 4.c000 phyxs control 2 phy xs control register 2 0f6f?h a r/w table 80 4.49153 4.c001 phyxs control 3 phy xs control register 3 0800?h a r/w table 81 4.49154 4.c002 phyxs err phy xs internal error code register 00fe?h a r/w table 82 4.49155 4.c003 phyxs idle phy xs internal idle code register 0007?h a r/w table 83 4.49156 4.c004 phyxs loop back phy xs loop back control register 0000?h a r/w table 84 4.49157 4.c005 pre_emph phy xs pre-emphasis level 0000?h a r/w table 85 4.49158 4.c006 equalization phy xs equalization control 0000?h a r/w table 87 4.49159 4.c007 test_flags phy xs receive path test & status flags 0000?h ro lh table 88 4.49160 4.c008 output ctrl output control and test function aaaa?h r/w table 89 4.49161 4.c009 half rate half rate clock mode enable 0000?h r/w table 71 4.49162 4.c00a los det phy xs status 4 los register 0000?h ro lh table 90 4.49163 4.c00b reserved phy xs control 4 txclk20 0000?h r/w table 91 4.49167 4.c00f soft reset reset (non mdio) 0000?h r/w sc table 46 bbt3821
46 ieee phy xs registers (4 .0 to 4.25/4.0019?h) note (1): this bit is latched low on a detected fa ult condition. it is set high on being read. note (1): these bits are latched high on any fault condition detected. they are reset low (cleared) on being read. they will als o be reset low on reading the lasi registers 1.9003?h (bit 10, see table 27) or 1.9004?h (bit 11, see table 28) table 75. ieee phy xs control 1 register mdio register address = 4.0 (4.0000?h) bit(s) name setting default r/w description 3.0.15 1.0.15 4.0.15 reset 1 = reset 0 = reset done, normal operation 0?b r/w sc writing 1 to this bit will reset the whole chip, including the mdio registers. 4.0.14 phy xs loopback 1 = enable loopback 0 = normal operation 0?b r/w enable phy xs loop bac k mode on all four lanes. 3.0.13 4.0.13 speed select 1 = 10gbps 1?b ro operates at 10gbps & above 4.0.12 reserved 00?h 4.0.11 lopower 0 = normal power 0?b r/w no low power mode, writes ignored 4.0.10:7 reserved 3.0.6 4.0.6 speed select 1 = 10gbps 1?b ro operates at 10gbps & above 3.0.5:2 4.0.5:2 speed select 0000 = 10gbps 0?h ro operates at 10gbps 4.0.1:0 reserved 0?b table 76. ieee phy xs status 1 register mdio register address = 4.1 (4.0001?h) bit name setting default r/w description 4.1.15:8 reserved 00?h 4.1.7 local fault 1 = phy xs local f ault 0 ro derived from register 4.0008?h 4.1.6:3 reserved 0?h 4.1.2 tx link up 1 = xgxs tx link up 0 = xgxs tx link down 1 (1) ro ll (1) ?up? means xaui-side signal level is ok, byte synch and lane-lane alignment have all occurred 4.1.1 lopwrable low power ability 0 ro device does not support a low power mode 4.1.0 reserved 0 table 77. ieee phy xs status 2 device present & fault summary register mdio register addresses = 4.8 (4.0008?h) bit name setting default r/w description 4.8.15:14 device present 10 = device present 10?b ro when read as ?10?, it indicates that a device is present at this device address 4.8.13:12 reserved 4.8.11 tx localflt 1 = tx local fault; on egress channel 0?b ro/ lh (1) lane alignment or byte alignment not done, or loss of signal. from reg. 4.24 4.8.10 rx localflt 1 = rx local fault; on ingress channel 0?b ro/ lh (1) pll lock failure (lack of rfcp/n signal) 4.8.9:0 reserved bbt3821
47 note (1): the status of these bits depends on the signal conditi ons. default shown is for normal operation. the bits contribute to the rx local fault bit, see table 77. vendor-specific phy xs registers (4.c000?h to 4.c00b?h) table 78. ieee 10gbase-x phy xgxs status register mdio register addresses = 4.24 (4.0018?h) bit name setting default r/w description 4.24.15:13 reserved 4.24.12 phy xs lane_align 1 = 4 lanes aligned 0 = lanes not aligned 1?b (1) ro 1 = four 3g receive lanes (on egress path) are aligned 4.24.11 test_pattern test pattern abilities 1?b ro 1 = the device is able to generate test patterns for 10gbase-x 4.24.10 phyxslpbk loopback ability 1?b ro 1 = device is able to loopback 4.24.9:4 reserved 4.24.3 lane3 sync 1 = lane is synchronized 0 = lane not synchronized 1?b (1) ro reflects the pcs_sync byte alignment state machine condition; not valid if not enabled in device (see table 80) 4.24.2 lane2 sync 1?b (1) ro 4.24.1 lane1 sync 1?b (1) ro 4.24.0 lane0 sync 1?b (1) ro table 79. ieee 10gbase-x phy xgxs test control register mdio register address = 4.25 (4.0019?h) bit name setting default r/w description 4.25.15:3 reserved 4.25.2 phy xs te s t p a t e n receive test pattern enable 0?b r/w 0 = do not enable receive test pattern 1 = enable receive test pattern 4.25.1:0 phy xs testpat type test pattern select (see table 72 for other test patterns generated by the bbt3821) 00?b r/w 11 = reserved 10 = mixed frequency test pattern (continuous /k/ = k28.5) 01 = low frequency test pattern (repeat 000001 1111 = k28.7) 00 = high frequency test pattern (repeat 0101010101 = d10.2) table 80. phy xs control register 2 mdio register address = 4.49152 (4.c000?h) bit name setting default (1) r/w description 4.49152.15:14 test mode 00?b 00?b r/w user should leave at 00?b 4.49152.13:12 reserved 4.49152.11 phy xs clock psync 1?b r/w 1 = synchronize/align four lanes 0 = do not synchronize/align four lanes 4.49152.10 phy xs codecena 0 = disable 1 = enable 1?b r/w internal 8b/10b codec enable/disable 4.49152.9:8 phy xs cdet[1:0] comma detect select. 11?b r/w these bits individually e nable positive and negative disparity ?comma? detection. 11 = enable both positive and negative comma detection 10 = enable positive comma detection only 01 = enable negative comma detection only 00 = disable comma detection 4.49152.7 phy xs dskw_sm_en 0 = disable (2) 1 = enable 0?b r/w enable de-skew state machine control (3) . forced enabled by phy xs xaui_en. may not operate correctly unless the phy xs pcs_sync_en bit is also set. 4.49152.6:5 phy xs rclkmode 11?b = local reference clock (4) 11?b r/w other values should only be used if incoming data is frequency-synchronous with the local reference clock (4) . bbt3821
48 note (1): the values may be overwritten by the auto-configure operation (see ?auto-configuring control registers? on page 16 and table 92 for details). note (2): these bits are overridden by phy xs xaui_en, see table 81 and table 65. note (3): these state machines are implemented according to 802.3ae-2002 clause 48. note (4): if the rclkmode bits are set to 10?b, the internal xgmii clock from the phy xs to the pcs is set to the recovered cloc k. if the phy xs clock psync bit is set (the default), the recovered clock from lane 0 is used for all four lanes, if cleared, or if the rclkmode bits are set to 01?b or 00 ?b, each lane uses its own recovered clock. if the incoming data is not frequency-synchronous with the local reference clock, data will be corrupted (occasional characters will be lost, or repeated). note (5): this bit name reflects the ?embedded? pcs func tion within an xgxs, see ieee 802.3 clause 47.2.1. 4.49152.4 phy xs pcs_sync_en (5) 0 = disable (2) 1 = enable 0?b r/w enable 8b/10b pcs coding synchronized state machine (3) to control the byte alignment (i eee ?code-group alignment?) of the high speed de-serializer 4.49152.3 phy xs idle_d_en 1 = enable 0 = disable 1?b r/w enables idle vs. non-idle detection for lane alignment. overridden by phy xs xaui_en, see table 88 4.49152.2 phy xs elst_en 1 = enable 0 = disable 1?b r/w enable the elastic function of the phy xs receiver buffer 4.49152.1 phy xs a_align_dis 1 = disable (2) 0 = enable 1?b r/w phy xs receiver aligns dat a on incoming ?/a/? characters (k28.3). if disabled (default), receiver aligns data on idle to non-idle transitions (if bi t 3 set). overridden by phy xs xaui_en, see table 81 4.49152.0 phy xs cal_en 1 = enable 0 = disable 1?b r/w enable de-skew calculator of phy xs receiver align fifo table 80. phy xs control register 2 (continued) mdio register address = 4.49152 (4.c000?h) bit name setting default (1) r/w description table 81. phy xs control register 3 mdio register address = 4.49153 (4.c001?h) bit name setting default (1) r/w description 4.49153.15 phy xs dc_o_dis 1 = disable, 0 = normal 0?b r/w phy xs dc offset disable 4.49153.14:13 reserved 4.49153.12 mf_sel select source of signals for four mf pins 0?b r/w 1 = select signals from pma/pcs to be output on mf pins 0 = select signals from phy xgxs to be output on mf pins 4.49153.11 phy xs xaui_en 1 = enable 0 = disable 1?b r/w enables all xaui features per 802.3ae-2002. it is equivalent to setting the configuration bits listed in table 65 (but does not change the actual value of the corresponding mdio registers? bits). 4.49153.10:8 phy_los_th 0?h = 160mv p-p 1?h = 240mv p-p 2?h = 200mv p-p 3?h = 120mv p-p 4?h = 80mv p-p else = 160mv p-p 000?b r/w set the threshold voltage for the loss of signal (los) detection circuit in phy xs. nominal levels are listed for each control value. note that the differential peak-to-peak value is twice that listed 4.49153.7 reserved 4.49153.6 phy xs akr_sm_en 1 = enable random a/k/r 0 = /k/ only (2) 0?b r/w enable pseudo- random a/k/r (3) in inter packet gap (ipg) on transmitter side (vs. /k/ only) 4.49153.5 phy xs trans_en 1 = enable 0 = disable (2) overridden by phy xs xaui_en, see table 65 0?b r/w this bit enables the transce iver to translate an ?idle? pattern in the internal fifos (matching the value of register 4.c003?h) to and from the xaui idle /k/ comma character or /a/, /k/ & /r/ characters. 4.49153.4 reserved 4.49153.3 phy xs tx_sdr phy xs receive data rate 0?b r/w 1 = phy xs takes data from pcs at half speed 0 = phy xs takes data from pcs at full speed bbt3821
49 note (1): the values may be overwritten by the auto-configure operation (see ?auto-configuring control registers? on page 16 and table 92 for details). note (2): these bits are overridden by phy xs xaui_en, see also table 65. note (3): this state machine is implemented according toieee 802.3ae-2002 clause 48. note (1): the values may be overwritten by the auto-configure operation (see ?auto-configuring control registers? on page 16 and table 92 for details). note (2): these bits are overridden to fe?h by phy xs xaui_en, see table 65 and table 81. note (1): the default value may be overwritten by the auto-configure operation (see ?auto-configuring control registers? on page 16 and table 92 for details). note (1): loopback is from xaui serial i/p to serial o/p. reco mmended use for test purposes only; no retiming or pre-emphasis is performed note (2): these values may be overwritten by the auto-configure operation (see ?auto-configuring control registers? on page 16 an d table 92 for details). 4.49153.2:0 mf_ctrl 0 = bist_err 1 = los 2,3 = reserved 4 = txfifo_err 5 = afifo_err 6 = efifo_err 000?b r/w control the meaning of multi-function pins mf[3:0] of the 4 lanes in the device selected by mf_sel above (bit 12) table 81. phy xs control register 3 (continued) mdio register address = 4.49153 (4.c001?h) bit name setting default (1) r/w description table 82. phy xs internal error code register mdio register, address = 4.49154 (4.c002?h) bit name setting default (1) r/w description 4.49154.15:8 reserved 4.49154.7:0 phy xs error desired value (2) fe?h r/w error code. these bits allow the internal fifo error control character to be programmed. table 83. phy xs internal idle code register mdio register address = 4.49155 (4.c003?h) bit name setting default (1) r/w description 4.49155.15:8 reserved 4.49155.7:0 phy xs xg_idle desired value 07?h r/w idle pattern in internal fifos for translation to/from xaui idles table 84. phy xs miscellaneous loop back control register mdio register address = 4.49156 (4.c004?h) bit name setting default r/w description 4.49156.15:13 reserved 4.49156.12 test lp 1 = enable 0?b (1) r/w serial host test loopback 4.49156.11 slp_3 1 = enable phy xs network loopback 0 = disable 0?b (2) r/w internal phy xs serial loop back enable for each individual lane. when high, it routes the internal xaui serial output to the serial input. 4.49156.10 slp_2 0?b (2) 4.49156.9 slp_1 0?b (2) 4.49156.8 slp_0 0?b (2) 4.49156.7:4 reserved 4.49156.3 plp_3 1 = enable system (?pcs?) parallel loopback 0 = disable 0?b (2) r/w pcs parallel loop back enable for each individual lane. when high, it routes the xaui serial input to the serial output via the full phy xs. 4.49156.2 plp_2 0?b (2) 4.49156.1 plp_1 0?b (2) 4.49156.0 plp_0 0?b (2) bbt3821
50 note (1): the values may be overwritten by the auto-configure operation (see ?auto-configuring control registers? on page 16 and table 92 for details). note (1): see note (2) to table 42 for a note about the equations and symbols used here. note (1): the value may be overwritten by the auto-configure operation (see ?auto-configuring control registers? on page 16 and t able 92 for details). note (1): these bits are latched high on any fault condition detected. they are reset low (cleared) on being read. they will als o be reset low on reading the lasi register 1.9004?h (see table 28) note (2): see also error counters in registers 3.c00d:e?h (table 73) table 85. phy xs pre-emphasis control mdio register address = 4.49157 (4.c005?h) bit name setting default (1) r/w description 4.49157.15:12 reserved 4.49157.11:9 pre_emp lane 3 see table 86 for settings 0?h r/w configure the level of phy xs pre-emphasis (nominal levels indicated) 4.49157.8:6 pre_emp lane 2 0?h 4.49157.5:3 pre_emp lane 1 0?h 4.49157.2:0 pre_emp lane 0 0?h table 86. phy xs xaui pre-emphasis control settings address 4.c005?h bits 2:0 pre-emphasis (1) (802.3ak) = (1-v low /v hi ) pre-emphasis value = (v hi / v low )-1 address 4.c005?h bits 2:0 pre-emphasis (802.3ak) = (1-v low /v hi ) pre-emphasis value = (v hi / v low )-1 000 0 0 100 0.50 1.00 001 0.17 0.20 101 0.53 1.28 010 0.28 0.39 110 0.57 1.33 011 0.44 0.79 111 0.60 1.50 table 87. phy xs equalization control mdio register address = 4.49158 (4.c006?h) bit name setting default (1) r/w description 4.49158.15:14 reserved 4.49158.3:0 phy xs eq_coeff 0?h = no boost in equalizer. f?h = boost is maximum 0?h r/w configuration of the phy xs equalizer table 88. phy xs receive path test and status flags mdio register address = 4.49159 (4.c007?h) bit name setting default r/w description 4.49159.15:12 test flags 0?h rolh special test use only 4.49159.11 efifo_3 1 = efifo error in lane 0 = no efifo error in lane 0?b rolh phy xs elasticity fifo overflow/underflow error detection (1) 4.49159.10 efifo_2 0?b 4.49159.9 efifo_1 0?b 4.49159.8 efifo_0 0?b 4.49159.7 code_3 1 = 10b/8b code error in lane 0 = no 10b/8b code error 0?b rolh phy xs 10b/8b decoder code violation detection (1) 4.49159.6 code_2 0?b 4.49159.5 code_1 0?b 4.49159.4 code_0 0?b 4.49159.3 bist_err_3 1 = bist error in lane 0 = no bist error in lane 0?b rolh lane by lane bist error checker indicator (1) (2) 4.49159.2 bist_err_2 0?b 4.49159.1 bist_err_1 0?b 4.49159.0 bist_err_0 0?b bbt3821
51 note (1): these bits are latched high on any los condition detected. they are reset low on being read. auto-configure register list table 89. phy xs output and test function control register mdio register address = 4.49160 (4.c008?h) bit name setting default r/w description 4.49160.15:14 reserved 10?b r/w test function, do not alter 4.49160.13 ena_3 enable lane 3 o/p 1?b r/w 0 = disable 4.49160.12:10 reserved 010?b r/w test function, do not alter 4.49160.9 ena_2 enable lane 2 o/p 1?b r/w 0 = disable 4.49160.8:6 reserved 010?b r/w test function, do not alter 4.49160.5 ena_1 enable lane 1 o/p 1?b r/w 0 = disable 4.49160.12:10 reserved 010?b r/w test function, do not alter 4.49160.1 ena_0 enable lane 0 o/p 1?b r/w 0 = disable 4.49160.0 reserved 0?b r/w test function, do not alter table 90. phy xs status 4 los detector register mdio register address = 4.49162 (4.c00a?h) bit name setting default r/w description 4.49162.15:4 reserved 00?b 4.49162.3 phy_los_3 1 = signal less than threshold 0 = signal greater than threshold 0?b ro/lh (1) loss of signal for lane 3 4.49162.2 phy_los_2 0?b loss of signal for lane 2 4.49162.1 phy_los_1 0?b loss of signal for lane 1 4.49162.0 phy_los_0 0?b loss of signal for lane 0 table 91. phy xs control register 4 mdio register address = 4.49163 (4.c00b?h) bit name setting default r/w description 4.49163.15:2 reserved 00?h 4.49163.1 txclk20 0 = disable 1 = enable 0?b r/w txclk20 pin output 4.49163.0 test internal 0?b r/w user must keep at 0?b table 92. auto-configure registers auto-configure pointer is ( s ), auto-configure size is ( n ), from 1.8106?h & 1.8105?h respectively nvr address target register bits address (1) target name (1) details dec hex dec hex s + 0 s + 0 4.49158.[3:0] 4.c006.[3:0] phy xs equalizer value table 87 s + 1 s + 1 4.49157.[7:0] 4.c005.[7:0] phy xs pre-emphasis lanes 1:0 table 85 s + 2 s + 2 4.49157.[15:8] 4.c005.[15:8] phy xs pre-emphasis lanes 3:2 s + 3 s + 3 1.49158.[3:0] 1.c006.[3:0] pma/pmd equalizer value table 43 s + 4 s + 4 1.49157.[7:0] 1.c005.[7:0] pma/pmd pre-emphasis lanes 1:0 table 41 s + 5 s + 5 1.49157.[15:8] 1.c005.[15:8] pma/pmd pre-emphasis lanes 3:2 s + 6 s + 6 1.36864.[6:0]. 1.9000.[6:0] lasi rx alarm control table 24 bbt3821
52 note (1): the 8 bits of the nvr register (7:0) are mapped to the listed bits of the target in order. unused bits are always at t he msb (bit 7) end. note (2): the target register pair are overlapped, ignoring the ?reserved? bits in one where used bits occur in the same locatio n in the other. thus the mapping from the nvr register is: 1.c001.[15:12], 3.c001.11, 1.c001.[10:8]. note (3): the mapping from the nvr register is: 1.c004.[11:8], 3.c004.[3:0] s + 7 s + 7 1.36865.[7:0] 1.9001.[7:0] lasi tx alarm control table 25 s + 8 s + 8 1.36865.[10:8] & 1.36866.[3:0] 1.9001.[10:8], 1.9002.[3:0] lasi tx alarm & lasi control table 25 & table 26 s + 9 s + 9 1.36870. 1.9006 dom tx flag control table 30 s + 10 s + a 1.36871. 1.9007 dom rx flag control table 31 s + 11 s + b 1.49170.[1:0], 1.49168.[5:0] 1.c012.[1:0], 1.c010.[5:0] gpio lasi & pin direction configuration table 49 & table 47 s + 12 s + c 1.49170.[11:8,5:2], 1.c012.[11:8,5:2] gpio lasi control table 49 s + 13 s + d 1.49170.[13:12], 1.49171.[5:0] 1.c012.[13:12], 1.c013.[5:0] tx_fault polarity, gpio lasi & output control table 49 & table 50 s + 14 s + e 1.49176 1.c018 dom control table 51 s + 15 s + f 1.49177.[7:0] 1.c019.[7:0] indirect dom mem address lane2 table 53 s + 16 s + 10 1.49177.[15:8] 1.c019.[15:8] indirect dom mem address lane3 s + 17 s + 11 1.49178.[7:0] 1.c01a.[7:0] indirect dom mem address lane0 s + 18 s + 12 1.49178.[15:8] 1.c01a.[15:8] indirect dom mem address lane1 s + 19 s + 13 1.49179.[7:0] 1.c01b.[7:0] indirect dom dev address lane2 table 54 s + 20 s + 14 1.49179.[15:8] 1.c01b.[15:8] indirect dom dev address lane3 s + 21 s + 15 1.49180.[7:0] 1.c01c.[7:0] indirect dom dev address lane0 s + 22 s + 16 1.49180.[15:8] 1.c01c.[15:8] indirect dom dev address lane1 s + 23 s + 17 1.49181.[7:0] 1.c01d.[7:0] optical i/f pin polarity control table 55 s + 24 s + 18 4.49152.[7:0] 4.c000.[7:0] phy xs control 2 table 80 s + 25 s + 19 4.49152.[15:8] 4.c000.[15:8] phy xs control 2 s + 26 s + 1a 4.49153.[7:0] 4.c001.[7:0] phy xs control 3 table 81 s + 27 s + 1b 4.49153.[15:8] 4.c001.[15:8] phy xs control 3 s + 28 s + 1c 4.49154.[7:0] 4.c002.[7:0] phy xs error code table 82 s + 29 s + 1d 4.49155.[7:0] 4.c003.[7:0] phy xs idle code table 83 s + 30 s + 1e 4.49156.[11:8,3:0] 4.c004.[11:8,3:0] phy xs loopback control table 85 s + 31 s + 1f 3.49152.[7:0] 3.c000.[7:0] pcs control 2 table 63 s + 32 s + 20 3.49152.[15:8] 3.c000.[15:8] pcs control 2 s + 33 s + 21 3.49153.[7:0] 3.c001.[7:0] pcs control 3 table 64 & table 39 (2) s + 34 s + 22 1:3.49153.[15:8] 1:3.c001.[15:8] pcs control 3/pma control 2 s + 35 s + 23 3.49154.[7:0] 3.c002.[7:0] pcs error code table 66 s + 36 s + 24 3.49155.[7:0] 3.c003.[7:0] pcs idle code table 67 s + 37 s + 25 1.49156.[11:8] 3.49156.[3:0] 1.c004.[11:8] 3.c004.[3:0] pcs/pma loopback control table 40 & table 68 (3) s + 38 s + 26 1.49163.[9:2] 1.c00b.[9:2] miscellaneous adjustments table 45 s + 39 s + 27 4.49163.[9:2] 4.c00b.[9:2] bitblitz internal test control table 91 table 92. auto-configure registers (continued) auto-configure pointer is ( s ), auto-configure size is ( n ), from 1.8106?h & 1.8105?h respectively nvr address target register bits address (1) target name (1) details dec hex dec hex bbt3821
53 jtag & ac-jtag operations five pins ? tms, tck, tdo, trst, a nd tdi ? support ieee standards 1149.1-2001 jtag and 1149.6-2003 ac-jtag testing. the jtag test capa bility has been implemented on all signal pins. note that the 1149.1-2001 specification has removed the previous require ment that the [000...0] instruction be an entry into ext est, and deprecated its use for anything but a non-test function (e.g. bypass). the bbt3821 fully conforms to this revision. the ac-jtag test capability has been implemented on the high-speed differential output and input terminals. the output configuration corresponds to fi gure 51 in ieee 1149.6-2003, except that there is no provision to bring the ?mission? signal into the scan chain, since this 3.125gbps signal has no meaningful value at the (asynchronous) jtag tck rate, and the bbt3821 does not support intest. the receiver configuration corresponds to figure 48, using the dc detection mode only, according to method 2 of 6.2.3.1 rule a), and omitting the components needed only for the unsupported intest instruction. the extest_pulse and extest_train instruct ion timings are illustrated in figures 37, 38 and 44 while the (dc) extest waveforms are indicated in figure 42 in ieee 1149.6-2003. provided that the tck period is sufficiently longer than the ac-coupling time constant, controlled by the (external) capacitors and the input impedance of the bbt3821, (see ieee 1149.6-2003 clause 6.2.3.1 rule k), the co mbination of (dc) extest and extest_pulse or extest_tra in scans can detect open or shorted capacitors or wires. the supported boundary scan operation instruction codes are listed in table 93: note (1): all non-listed codes are also bypass. the manufacturers id code returned when reading the id code from the jtag pins is as follows:- v0006351?h where ?v? is an internal 4-bit version number. consult the ?intersil corporation contact information? on page 75 for information as to the meaning of the revision number. note that the jtag and ac-jtag capability is not currently tested in production. bist operation in addition to the low, mid and high frequency test patterns defined in ieee 802.3ae-2002, which are injected (at the 10- bit level) directly into the serializers, and controlled via the ?ieee 10gbase-x pcs test control register ? on page 40 and the ?ieee 10gbase-x phy xgxs test control register ? on page 47, and to further facilitate the exercise of all the bt3821 blocks, t he device includes a built in self test (bist) f unction. the bist data package generator sends out a continuou s data stream to emulate network traffic. the available bi st data patterns are enabled via the bits in table 72. the patterns available are: 1. crpat pattern per i eee802.3ae-2002 annex 48a 2. cjpat pattern per ieee8 02.3ae-2002 annex 48a 3. a full prbs23 pattern (2 23 ?1 coded bytes, 10 times that many bits) with nine /k/ ?comma? characters as interval on each xaui/cx4 lane. 4. a short pseudo-random data pattern (13458 byte long) with nine /k/ ?comma? characters as interval on each xaui/cx4 lane. 5. emulation of an ethernet jumbo frame: ||s|| + preamble + random data (4 x 13458 byte long) + ||t|| + ipg; the ?prbs23?-based patterns are derived from a prbs generator that, after an inter-packet gap (?ipg?) of 9 /k/ characters, creates a pseudo-random 2 23 ? 1 byte sequence. the full sequence is used for the ?prbs23? pattern, while the ?sho rt prbs23? pattern is truncated after 13458 bytes. each will start again from the beginning, repeating indefinitely. this pattern is generated on each lane, and checked (except for the /k/s, of which one is required for byte synchronization, but all the others are ignored) in the same way. the ?jumbo ethernet packet? is similar, except that the ?short prbs23? pattern is preceded by an /s/ & one preamble on lane 0, two preambles on lanes 1 & 2, and a preamble and sfd on lane 3, and followed by a /t/ on lane 0. apart from providing byte sync (byte alignment), the /k/- filled ipg allows for lane alignment (using the idle-to- nonidle transition alignment engine) and elasticity (by deleting or adding the requisite number of /k/s). the latter, in particular, allows one bbt3821 to check the ?short prbs23? or ?jumbo ethernet packet? generated by another bbt3821 running on an independent clock within 100 ppm. the full prbs23 pattern could be over 300 bytes off in one repeat table 93. jtag operations instruction code bypass (1) 0000 sample/preload 0001 highz 0010 clamp 0011 id code 0110 extest 1000 udr0 1001 extest_pulse 1011 extest_train 1100 bypass 1111 bbt3821
54 under these circumstances, greatly exceeding the elasticity fifo?s range, unless the cl ocks were synchronized. the cjpat and crpat patterns ar e those defined by ieee 802.3ae-2002 annex 48. either the bist_en bit (see table 72 or the bist_ena pin (see table 99 on page 56) will cause the serial transmitter selected by the bist_dir bit to put out the pattern selected by the bist_pat bits (see table 72). the bist_det bit will enable the serial receiver selected by the bist_src bit to search its incoming bit stream for the pattern (separately) selected by the bist_chk bits (see table 72). once the comma group or ipg has set the byte alignment, the bist error detector will be enabled, and the decoded pattern will be then be checked. any bit error will set the error detector for the corresponding lane, and increment the bist_err_cnt counters (see table 73). these detectors may be monitored via the mf[3:0] pins (see table 99) and both they and the counters may be read via the mdio system (see table 81). the separate setup for bist generation and checking means that two bbt3821s may be tested with a different pattern in each direction on the link between them. the signal flows provided for these bist patterns are shown in figure 6. the generator output may be injected (in place of the ?normal? signal flow) into the akr randomizer in either the pcs or phy xs, as controlled by the "bist control register" (see table 72). the signal may be looped back using the pma or phy xs loopbacks (respectively), and checked at the output of the respective elastic fifo, or continue on to the other loop back, and checked at the output of the other elastic fifo. the internal loopback(s) may be replaced by external loopbacks, and in each ?full loop? case this will test virtually the complete device; if both possible full loops are checked, both comple te signal paths are tested. note that if any external loopback changes the clock domain, the full ?prbs23? pattern cannot be checked. pcs // = phy xs loopback 4.c004 & ~3.0.14) pcs // network loopback (3.c004) cdr deserializer & comma detector 10b/8b decoder rx fifo deskew serializer 8b/10b encoder, akr generator txfifo & error and orderset detector txpn p/n rcxn p/n equalizer signal detect cdr deserializer & comma detector 10b/8b decoder rx fifo deskew serializer 8b/10b encoder, akr generator txfifo & error and orderset detector rxpnp/n equalizer signal detect tcxn p/n pma loopback (1.0.14 & 1.c004) phy xs (serial) loopback (4.0.14 & 4.c004) ingress egress ingress egress hf, lf, mixedf generator hf, lf, mixedf generator crpat, cjpat, prbs23 checker crpat, cjpat, prbs23 generater ieee reg 4.25 ieee reg 3.25 vendor reg 3.c003 vendor reg 3.c003 device address 3 pcs device address 4 phy xgxs d e v i c e a d d r e s s 1 p m a / p m d only one lane of four shown only one lane of four shown figure 6. block diagram of bist operation bbt3821
55 pin specifications table 94. clock pins pin# name type description t9/t8 rfcp/rfcn input lvpecl differential reference input clock. the reference input clock frequency is line rate clock frequency divided by 20 (full rate mode) or 10 (half rate mode). the pins are internally biased at vdda/2, and should be ac coupled. c10 txclk20 output 1.5v cmos transmit clock output. divided-by-20 transmit clock output. table 95. xaui (xenpak/xpak/x2) side serial data pins pin# name type description t14/t15 txp0p/txp0n output cml transmit differential pairs, lane 0 to 3. cml high speed serial outputs. p14/p15 txp1p/txp1n m14/m15 txp2p/txp2n k14/k15 txp3p/txp3n h14/h15 rxp0p/rxp0n input cml receive differential pairs, lane 0 to 3. cml high speed serial inputs. differentially terminated at 100 ? f14/f15 rxp1p/rxp1n d14/d15 rxp2p/rxp2n b14/b15 rxp3p/rxp3n table 96. pma/pmd (cx4/lx4) side serial data pins pin# name type description a2/a3 tcx0p/tcx0n output cml transmit differential pairs, lane 0 to 3. cml high speed serial outputs. c2/c3 tcx1p/tcx1n e2/e3 tcx2p/tcx2n g2/g3 tcx3p/tcx3n r2/r3 rcx0p/rcx0n input cml receive differential pairs, lane 0 to 3. cml high speed serial inputs. differentially terminated at 100 ? n2/n3 rcx1p/rcx1n l2/l3 rcx2p/rcx2n j2/j3 rcx3p/rcx3n table 97. jtag interface pins pin# name type description d12 tdi input (with pullup) jtag input data. 1.5v cmos b12 tdo output (open drain) jtag output data. 1.5v cmos, 2.5v tolerant d8 tms input (with pullup) jtag mode select. 1.5v cmos c12 tclk input (with pulldown) jtag clock. 1.2v cmos, 2.5v tolerant, with schmitt trigger c8 trstn input (with pullup) jtag reset. 1.5v cmos bbt3821
56 table 98. management data interface pins pin# name type description p11 mdio i/o (open drain output) management address/data i/o. 1.2v cmos input, 2.5v tolerant r11 mdc input management interface clock. 1.2v cmos, 2.5v tolerant, with schmitt trigger r12 padr[4] input management port address setting 1.2v cmos t12 padr[3] p12 padr[2] n12 padr[1] t11 padr[0] table 99. miscellaneous pins pin# name type description n11 mf[0] output 1.5v cmos multi-function outputs, lanes 0 - 3 . the functions of these pins are enabled via the mdio interface. the default condition for these pins is ph y xgxs bist_err. see table 81 (bits mf_sel and mf_ctrl) for further details. p10 mf[1] b9 mf[2] a10 mf[3] n10 rstn input chip reset (fifo clear) assert rstn for at least 10s from power up. active low. schmitt trigger input, 1.2v cmos, 2.5v tolerant. d10 bist_ena input (with pulldown) built-in self test enable- active high. when high, enables internal 2 23 -1 byte prbs test function generator and checker. 1.5v cmos a11 lx4_mode input (with pulldown) cx4/lx4 mode select. when high, lx4 mode is selected. when low, cx4 mode is selected. this pin decides the trigger sour ces of lasi, and the default pre-emphasis and equalization strength of the high speed seri al port on the pma/pmd side. 1.5v cmos b11 lasi output (open drain) link alarm status interrupt request . when low, pin indicates the existence of an incorrect condition. an external 10-22k ? pull-up to 1.2v or 1.5v is recommended. 1.2v cmos, 2.5v tolerant. d7 optxlbc (1) input tx laser bias current. optical monitoring input. active le vel is latched into register bit 1.36868.9 and can be configured to trigger lasi. when this pin is not driven by an external device, it should be pulled inactive (defau lt down). 1.5v cmos, 2.5v tolerant. d5 opttemp (1) input transceiver temperature. optical monitoring input. active le vel is latched into register bit 1.36868.8 and can be configured to trigger lasi. when this pin is not driven by an external device, it should be pulled inactive (defau lt down). 1.5v cmos, 2.5v tolerant. d6 optxlop (1) input tx laser output power. optical monitoring input. active le vel is latched into register bit 1.36868.7 and can be configured to trigger lasi. when this pin is not driven by an external device, it should be pulled inactive (defau lt down). 1.5v cmos, 2.5v tolerant. n8 tx_fault (2) input tx fault condition. transmitter (egress) external fault input. active level is latched into register bits 1.10 and 1.36868.6 and can be configur ed to trigger lasi. when this pin is not driven by an external device, it should be pulled inactive (default down). 1.5v cmos, 2.5v tolerant. c5 oprxop (1) input receive optical power. optical monitoring input 4. active le vel is latched into register bit 1.36867.5 and can be configured to trigger lasi. when this pin is not driven by an external device, it should be pulled inactive (defau lt down). 1.5v cmos, 2.5v tolerant. a6 oprlos[3] (1) input optical receiver loss of signal. optical monitoring input 5 ? 8. active (loss) levels are latched into register 1.10 and can be configured to trigger lasi. when these pins are not driven by an external device, they should pulled inactive ( default down). 1.5v cmos, 2.5v tolerant. a5 oprlos[2] (1) a7 oprlos[1] (1) b7 oprlos[0] (1) d11 xp_ena input xenpak enable. enable xenpak support. active high. activates 2-wire serial bus interface. 1.5v cmos, 2.5v tolerant. bbt3821
57 note (1): active level of these pins is controlled by register 1.49181 (1.c01d?h), see table 55. if unused, the tx_enc pin can be tied high, and the register bit not altered. other unused input pins should be tied low, and the corresponding register bit not altered, so the default value of th e register will allow byte synch and cause a ?no fault? indication in the lasi alarm status registers on reset. see also table 12, table 27 and table 28. note (2): active level of this pin is controlled by register 1.49170 (1.c012?h), see table 49. otherwise note 1 applies. d9 tx_enc (1) input transmit enable input from xenpak module input ?tx on/off?. controls tx_ena[3:0]. for normal operation, should be pulled active (default up). 1.2v cmos b5 tx_ena[3] (1) output (open drain) transmit laser driver enables. they are set active only when tx_enc pin is active and the corresponding bits in register 1.9 are set low. during reset stage, these pins are always low. 1.5v cmos, 2.5v compatible. b6 tx_ena[2] (1) t5 tx_ena[1] (1) r5 tx_ena[0] (1) table 99. miscellaneous pins (continued) pin# name type description table 100. i 2 c 2-wire serial data interface pins pin# name type description p9 sda i/o (open drain) i 2 c serial address/data i/o 1.5v cmos, 2.5v tolerant and compatible p8 scl i/o (open drain) i 2 c serial interface clock. 1.5v cmos, 2.5v tolerant and compatible c7 wrtp input i 2 c serial interface write protection. when high, no write to protected xenpak basic nvr area is allowed. 1.5v cmos, 2.5v tolerant r6 gpio[4] i/o (open drain) general purpose i/o can be used for optical monitoring and status reporting, and to trigger lasi, or for ex ternal control functions. 1.5v cmos, 2.5v tolerant and compatible p7 gpio[3] n7 gpio[2] n6 gpio[1] p6 gpio[0] table 101. voltage supply pins pin# name type description c6, c13, h13, j4, n5, n13 vddpr supply 2.5v protection voltage supply. may be same level as vdd if no inputs or outputs go above the vdd level. a4, a8, a9, a12, a13, b10, n9, p4, p5 vdd supply 1.5v digital and core supply b4, c4, c14, d4, d13, e4, e13, f4, f13, g4, g13, k4, k13, l4, l13, m4, m13, n4, p13, r4, r13, t4, t13 vdda analog supply 1.5v analog supply. should be decoupled from vdd r7, t7 vddav analog supply analog supply for vco. should be decoupled from vdda r10, t10 vddac analog supply analog supply for cmu. should be decoupled from vdda a1, a14, a15, a16, b1, b2, b3, b8, b13, b16, c1, c9, c11, c15, c16, d1, d2, d3, d16, e1, e14, e15, e16, f1, f2, f3, f16, g1, g14, g15, g16, h1, h2, h3, h4, h16, j1, j13, j14, j15, j16, k1, k2, k3, k16, l1, l14, l15, l16, m1, m2, m3, m16, n1, n14, n15, n16, p1, p2, p3, p16, r1, r8, r9, r14, r15, r16, t1, t2, t3, t6, t16 gnda ground ground. electrically well grounded. analog and digital grounds are tied in the device, but it is recommended that some separation be provided in the pcb planes outside the device, to mi nimize the coupling between digital signals and the analog sect ions of the device. bbt3821
58 pin diagram 17x17mm (16*16 ball ma trix) 192-pin ebga-b package figure 7. top view of pinout abcdefghjklmnprt 16 gnda gnda gnda gnda gnda gnda gnda gnda gnda gnda gnda gnda gnda gnda gnda gnda 16 15 gnda rxp3 n gnda rxp2 n gnda rxp1 n gnda rxp0 n gnda txp3 n gnda txp2 n gnda txp1 n gnda txp0 n 15 14 gnda rxp3 p vdda rxp2 p gnda rxp1 p gnda rxp0 p gnda txp3 p gnda txp2 p gnda txp1 p gnda txp0 p 14 13 vdd gnda vdd pr vdda vdda vdda vdda vdd pr gnda vdda vdda vdda vdd pr vdda vdda vdda 13 12 vdd tdo tclk tdi padr 1 padr 2 padr 4 padr 3 12 11 lx4_ mode lasi gnda xp_e na mf0 mdio mdc padr 0 11 10 mf3 vdd txcl k20 bist_ ena rstn mf1 vdda c vdda c 10 9 vdd mf2 gnda tx_e nc vdd sda gnda rfcp 9 8 vdd gnda trst n tms tx_f ault scl gnda rfcn 8 7opr los1 opr los0 wrtp optx lbc gpio 2 gpio 3 vdda v vdda v 7 6opr los3 tx_e na2 vdd pr optx lop gpio 1 gpio 0 gpio 4 gnda 6 5opr los2 tx_e na3 oprx op opt temp vdd pr vdd tx_e na0 tx_e na1 5 4 vdd vdda vdda vdda vdda vdda vdda gnda vdd pr vdda vdda vdda vdda vdd vdda vdda 4 3tcx0 n gnda tcx1 n gnda tcx2 n gnda tcx3 n gnda rcx3 n gnda rcx2 n gnda rcx1 n gnda rcx0 n gnda 3 2tcx0 p gnda tcx1 p gnda tcx2 p gnda tcx3 p gnda rcx3 p gnda rcx2 p gnda rcx1 p gnda rcx0 p gnda 2 1 gnda gnda gnda gnda gnda g nda gnda gnda gnda gnda gnda gnda gnda gnda gnda gnda 1 abcde fgh jklmnprt bbt3821
59 package dimensions figure 8. ebga-192 package dimensions bbt3821
60 electrical characteristics absolute maximum ratings note (1): these ratings are those which if exceeded may cause per manent damage to the device. operation at these or any other co nditions in excess of those listed under operating conditions below is no t implied. continued exposure to these ratings may reduce device reliability. operating conditions all standard device specifications assume t c = 0c to +85c, v ddac = v ddav = v dd = v dda = 1.5v 5%, v ddpr = v dd or 2.4v 0.1v, unless otherwise specified. the low power device specifications assume t c = 0c to +85c, v ddac = v ddav = v dd = v dda = 1.355v 4%, v ddpr = v dd or 2.4v 0.1v, unless otherwise specified. note (1): the v ddpr supply should be tied to a level at or above v dd , and at the highest level expected on any ?2.5v to lerant? control pin, consistent with the above ratings. note (2): for reference only. all testing is performed based on case temperature. note (1): the ?max? value is at the maximum supply voltages, while the ?typ? value is at the nominal supply voltages. the power dissipation is not significantly affected by the v ddpr supply (see table 111 for the distribution of power between the supplies). note (2): the operating power varies slightly with the data pattern. the part is tested using a prbs23 pattern. table 102. absolute maximum ratings symbol parameter min max units v ddpr 2.5v protection power supply voltage -0.5, v dd - 0.5 2.6, v dd + 2.0 v v dda, v dd, v ddac, v ddav all other power supply voltages -0.5 1.65 v v incml cml dc input voltage -0.5 v dd + 0.5 v i outcml cml output current - 50 +50 ma v incms1 1.2v cmos input voltage -0.5 v dd + 0.5 v v incms2 1.5v cmos input voltage -0.5 v dd + 0.5 v v incms3 2.5v tolerant cmos input voltage -0.5 2.6 v t stg storage temperature - 55 125 c t j junction temperature - 55 125 c t sol soldering temperature (10s) 220 c v esd maximum input esd (hbm) -2000 2000 v table 103. recommended operating conditions symbol parameter min nom max units v dda v ddav , v ddac & v dd core and serial i/o power supply voltages (standard device) 1.425 1.5 1.575 v (low power device) 1.300 1.355 1.410 v v ddpr control i/o protection power supply voltage v dd (1) 2.5 v t a ambient operating temperature (2) 025+70c t c case operating temperature 0 +85 c table 104. power dissipation and thermal resistance symbol parameter typ (1) max (1) units pd power dissipation (2) (standard device) 1650 1830 mw (low power device) 1350 1475 mw jc thermal resistance, junction to case 2.0 c/w ca thermal resistance, case to ambient (sti ll air, gap filler & cold plate) 13.0 c/w ca thermal resistance, case to ambient (still air only) 31.0 c/w bbt3821
61 dc characteristics note (1): measured at tp3 as defined in the ieee 802.3ak-2004 s pecifications. this value is needed in each ipg to maintain the s ig_det function active. the bbt3821 will provide a ber < 1 in 10 -12 under the conditions of clause 54.6.4.1 of the specification. note (2): measured at tp2 as defined in the ieee 802.3ak-2004 specifications. note (3): cx4 mode not specified for low power vdd = 1.35v operation; ?standard device? conditions are required. note (1): bbt3821lp-jh only. note (1): measured using cjpat. note (1): xenpak msa recommended for lasi pin. note (2): for mdio and lasi pins. note (3): only for rstn and mdc pins. table 105. pma serial pin i/o electrical specifications, cx4 mode (3) symbol parameter min typ max units v p-pin peak-to-peak differential voltage input requirement (1) 100 >60 2000 mv v p-pout2 peak-to-peak differential voltage output (z o = 100 ? differential load), definit ion as per ieee 802.3ak-2004 (2) , standard device only 800 1000 1200 mv ? v p-pout2 difference between v p-pout2 from lane to lane on any group (cx4 or xaui) (2) 75 150 mv v cmo output common mode voltage v dd -.5 v v cmi internal input common mode voltage 0.4 v table 106. pma serial pin i/o elec trical specifications, lx4 mode symbol parameter units min typ max v p-pin peak-to-peak differential voltage input requirement mv 100 >60 2000 v p-pout2 peak-to-peak differential voltage output (z o = 100 ? differential load) (standard) mv 800 1100 1600 (lowpower) (1) mv 650 v cmo output common mode voltage v v dd -.5 v cmi internal input common mode voltage v 0.4 table 107. phy xs serial pin i/o electrical specifications, xaui mode symbol parameter min typ max units v p-pin peak-to-peak differential voltage input requirement 100 >60 2000 mv v p-pout2 peak-to-peak differential voltage output (z o = 100 ? differential load), definition as per 802.3ae-2002 800 1200 1600 mv v cmo output common mode voltage v dd -.6 v v cmi internal input common mode voltage 0.4 v table 108. external 1.2v cmos open drain i/o electrical specifications v pull = external pullup voltage, not to exceed v dd symbol parameter min typ max units r pullup external pullup resistor for open drain o/p (1) 10 22 k ? v ol output low voltage level (iol = 4ma) (2) 0 120 200 mv v oh output high voltage level (1) v pull -0.4 v pull v v il input low voltage level -0.2 0.360 v v ih input high voltage level 0.840 v dd +0.2 v v hyst hysteresis on schmitt trigger inputs (3) 100 150 mv i il input low current, v in = 0.0v -80 a i ih input high current, v in = v dd .1 10 a bbt3821
62 note (1): assumes pullup to v dd . note (2): for mf[3:0] and txclk20 pins only note (3): for tdi, tms, trstn pins only note (4): for tclk, bist_ena, lx4_mode pins only note (1): input voltage beyond r pullup pullup resistor; pin should not exceed v ddpr value note (2): only tck pin. note (1): the maximum limit is measured using a prbs23 pattern. t he supply current for the crpat test pattern is very slightly l ower, and for the cjpat pattern is typically 20ma lower. note (2): this maximum limit refers to the lowpower part only, and is measured at 1.410v. table 109. 1.5v cmos input/output electrical specifications symbol parameter min typ max units v ol output low voltage level (i ol = 2 ma) 0 200 400 mv v oh open drain output high voltage level (1) v dd -0.4 v dd v v oh output high voltage level (i oh = 2ma) (2) v dd -0.4 v dd v v il input low voltage level -0.2 0.3*v dd v v ih input high voltage level 0.7*v dd v dd +0.2 v i ilpu input low current, v in = 0.0v, with pull-up (3) -100 40 a i il input low current, v in = 0.0v -10 -1 a i ihpd input high current, v in = v dd , w. pull-down (4) 100 200 a i ih input high current, v in = v dd 110 a table 110. 2.5v tolerant open drain cmos input/output electrical specifications v pull = external pullup voltage, not to exceed 2.5v or v ddpr symbol parameter min typ max units r pullup external pullup resistor for all i/p, open drain o/p 10 15 22 k ? v ol output low voltage level (i ol = 2ma) 0 200 400 mv v oh output high voltage level (ioh = 100a) least of 2.5 & v pull -0.4 2.5 v pull v v il input low voltage level -0.2 0.3*v dd v v ih input high voltage level 0.7*v dd v ddpr +0.2 (1) v v hyst hysteresis on schm itt trigger inputs (2) 100 150 mv i il input low current, v in = 0.0v -80 a i ih input high current, v in = 1.5v .1 10 a input high current, v in = 2.6v or v ddpr 100 a table 111. other dc electrical specifications symbol parameter min typ max units i ddav + i dd + i dda + i ddac total 1.5v supply current, t a = 25c 1100 ma total 1.5v supply current, t c = 0 to 85c (1) 1162 (1) ma total 1.355v supply current, t c = 0 to 85c (1,2) 1016 1046 (1,2) ma i ddpr protection voltage supply current 0.1 5 ma i dda analog supply current 810 ma i ddav , i ddac vco, cmu supply current 35 ma i dd digital core supply current 210 ma bbt3821
63 ac and timing characteristics all specifications assume t c = 0c to +85c, and v ddac = v ddav = v dd = v dda = 1.5v 5% (for the standard device) or v ddac = v ddav = v dd = v dda = 1.35v 4%(for the low power device), v ddpr between v dd and 2.5v, unless otherwise specified. note (1): system requirements are normally much more restrictive, typically 100 ppm. this specification refers to the full ref erence clock frequency range over which the bbt3821 will operate. note (2): single-ended peak-to-peak swing. note (1): strictly the 1100 pattern causes a small additional non- random jitter, so that the true random jitter is slightly less than that shown. note (2): parameter is guaranteed by design note (1): jitter specifications include all but 10 -12 of the jitter population. note (2): near end driven by bbt3821 tx without pre-emphasis. table 112. reference clock requirements symbol parameter min typ max units f ref ref clock frequency range (1) 124.4 159.375 mhz ? f ref ref clock frequency offset -100 +100 ppm t refrf ref clock rise and fall time 1.5 ns dtc ref ref clock duty cycle 45 50 55 % ? v ref ref clock voltage swing (2) 300 1000 mv v cm internal common mode voltage v dd /2 v table 113. transmit serial differential ou tputs (see figure 9, figure 10 and figure 11) symbol parameter min typ max unit tcxnp/n and txpxp/n output data rate 2.448 3.1875 gbps t dr differential rise time (20%-80%) 60 110 130 ps t df differential fall time (20%-80%) 60 110 130 ps t dtol differential skew tolerance tbd ps t ods lane to lane differential skew (2) 15 ps differential output impedance 100 ? differential return loss (to 2.5ghz) 10 db tx rj random jitter (rms, 1100 pattern) (1) 2.488gbps 2 4.5 ps 3.125gbps 2.5 4.5 ps 3.1875 tbd tbd ps total jitter (rms, prbs 7 pattern) 2.488gbps 8 ps 3.125gbps 6 8 ps 3.1875 8 ps table 114. receive serial differential in put timing requirements (see figure 11) symbol parameter min typ max units rcxnp/n & rxpnp/n input data rate 2.448 3.1875 gbps input rate deviation from reference clock -200 +200 ppm bit synchronization time 2500 bits frequency lock after power-up 2 s t dtol input differential skew 75 ps t dj deterministic jitter (1,2) 2.488gbps tbd ui 3.125gbps 0.7 ui 3.1875 tbd ui t ji total jitter tolerance 2.488gbps tbd ui 3.125gbps 0.88 ui 3.1875 tbd ui bbt3821
64 note (1): the bbt3821 will accept a much higher mdc clock rate and shorter hi and lo times than the ieee802.3 specification (sec tion 22.2.2.11) requires. such a faster clock may not be acceptable to other devices on the interface. note (2): the bbt3821 mdio registers will not be written until two mdc clocks have occurred after the frame end. these will norm ally count toward the minimum preamble before the next frame, except in the case of writing a reset into [1,3,4].0.15, see figure 17 . note (1): assuming rfcp-n clock is 156.25mhz, and register bits 1.8005.6:4 set for 400khz (table 20). scl clock period scales wit h reference clock frequency. also, per the i 2 c specification, the scl ?high? time is stretched by the time taken for scl to go high after the bbt3821 releases it, to allow an i 2 c slave to demand additional time. any rc delays on the scl line will add to the scl ?high? time, in increments of approximately 100ns. table 115. mdio interface timing (from ieee802.3ae) (see figure 15 to figure 17) symbol parameter min typ max unit t mdcd bbt3821 mdio out delay from mdc 0 5.0 300 ns t mds setup from mdio in to mdc 10 1.5 ns t mdh hold from mdc to mdio in 10 1.5 ns t mdc clock period mdc (1) 100 400 ns t mdv mdc clock hi or lo time (1) 20 160 ns t update delay from last data bit to register update (2) 2t mdc c md input capacitance 10 pf table 116. reset and mdio timing (see figure 17) symbol parameter min typ max units t rstbit reset bit active width 2 t mdc t mdrst delay from reset bit to first active preamble count 240 256 282 t refclk table 117. reset and i 2 c serial interface timing (see figure 18 and figure 24) symbol parameter min typ max units t reset rstn active width 10 s t wait delay from rstn to i 2 c scl start 10 ms t train i 2 c ?training? (external reset) 30 t clah_l t clah_l period of i 2 c scl clock line (400khz) 2.5 s (1) t scl_dav setup from i 2 c sda data valid to scl edge 100 ns t sda_clv setup, hold from sda for start, stop 600 ns c i2c input capacitance 10 pf bbt3821
65 timing diagrams figure 9. differential output signal timing figure 10. lane to lane differential skew figure 11. eye diagram definition tcx[3:0]p, txp[3:0]p t dtol t f tcx[3:0]p-n, txp[3:0]p-n tcx[3:0]n, txp[3:0]n t r t dr t df t ods txp[3:0]p/n, tcx[3:0]p/n txp[3:0]p/n, tcx[3:0]p/n vcm vpp (single-ended) total jitter eye width unit interval (ui) bbt3821
66 figure 12. byte synchronization figure 13. lane-lane alignment operation figure 14. retransmit latency internal fifo data rcx[3:0]p-n, rxp[3:0]p-n internal byte clock rt sync data not comma none random comma idle error comma idle data rt lat refclk rxclk rt skewin serialized rcx0 data idle data data data data idle align serialized rcx2 ----to---- ----to---- serialized rcx3 align data idle data data data idle idle align data data data data data idle idle data idle idle idle data idle idle data idle idle idle data idle idle rt skew serialized txp0 serialized txp3 rcx[3:0] -> txp[3:0] shown, rxp[3:0] -> tcx[3:0] is identical rt lat data data idle rcx[3:0]p-n, rxp[3:0]p-n idle txp[3:0]p-n, tcx[3:0]p-n bbt3821
67 figure 15. mdio frame and register timing figure 16. mdio interface timing t preamble frame mdio (from sta) mdc t update register contents mdio (from mmd) read operations shown in red idle/preamble prev st op prt/dev ad address/data preamble ta new data old data mdc t mdc t mdcd t mdsu t mdh mdio sta sourced mdio mdd sourced sta ? mmd ta (for read ops) mmd ? sta bbt3821
68 figure 17. mdio timing af ter soft reset (d.0.15) figure 18. beginning i 2 c nvr read at the end of reset figure 19. i 2 c bus interface protocol bit reset d.0.15 reset mdio engine engine reset, ignores preamble 1 st preamble bit mdc t rstbit t mdrst (internal states, not observable) t wait rstn scl auto-config data default data t config control registers sda t train (done) rst train read nvr read dom wait wait condition t wait t update t reset scl sr or p msb acknowledgement signal from slave acknowledgement signal from receiver byte complete, interrupt within slave clock line held low while interrupts are served 1 2 7 8 9 1 2 3 - 8 9 ack ack s or sr start or repeated start condition stop or repeated start condition sda bbt3821
69 figure 20. nvr/dom sequential read operation figure 21. nvr sequential write one page operation figure 22. i 2 c single byte read operation figure 23. single byte write operation a c k a c k p w a c k s s r slave addr slave addr read data read data a c k last read data no ack s word addr a c k a c k a c k read data a c k a c k p w a c k s slave addr write data a c k last write data no ack word addr a c k a c k write data a c k write data write data a c k p a c k s s r slave addr word addr read data no ack a c k w slave addr a c k p w a c k s word addr write data a c k w slave addr bbt3821
70 figure 24. i 2 c operation timing applications information cx4/lx4/xaui re-timer setup this section discusses the setup for the bbt3821 to be used as a xaui/cx4/lx4 retimer. the various descriptions and comments further assume that the device is initially configured in the default condition (i.e. exactly as found after a hardware reset). the bist_ena pin should be pulled low (to gnd); the pin has an internal pulldown to this value. the lx4_mode select pin should be tied to the appropriate level, depending on whether the bbt3821 is interfaced to a cx4 connection, or a xaui/lx4 interface (where it is assumed that the electro-optical interface is xaui-compatible). although the bbt3821 will come out of reset with cx4 or xaui-directed values, some of t hese default register settings may need to be changed, for optimum operation in any specific application. all of these may be set via the auto- configure operation (see ?auto-configuring control registers? on page 16). the default values of pre-emp hasis and receive equalization set by the lx4_mode select pin may need to be adjusted, particularly if the serial 3gbps pcb traces on the ?host? side (the xaui or the xenpak/xpak/x2 side) are long, (in which case the phy xs values may need adjustment), or if the connection to a cx4 connector or laser driver and photo detector and limiting amplifier involve extra connectors, long traces, or enhanced edge rates (in which case the pma/d values should be adjusted). the default value of the pma/d and phy xs xaui_en bits is set at ?1?, and for normal xaui or cx4/lx4 operation, this is usually the best setting for this use. byte alignment will follow the ieee 802. 3ae pcs sync spec ification, lane alignment will follow the deskew algorithm in the same specification, and the pseudo -random /a/k/r/ generation in idle will also be performed according to the same specifications. for certain non-10gbase-x uses, or for debug and problem analysis purposes, and in particular for certain bist testing, it may be advantageous to change some of the settings. to achieve this, the relevant (p ma/d and/or phy xs) xaui_en bits must be turned off (to ?0?), since otherwise they will override many of the other regist ers? bits (see table 65). for instance, if it desirable to change byte alignment to a simpler algorithm than the ieee-defined one (if, for example, only three of the four lanes are working), the pcs_sync_en bit(s) (table 63 and/or table 80) may be turned off, and (with the respective xaui_en bit off), byte (code group) alignment on the working lanes will now function. similarly, setting the a_align_dis bit in the pcs/phy xs control register 2 ([3,4].c000?h) will cause lane alignment to occur on idle to non-idle transitions across all four lanes, instead of lane alignment on ||a|| (k28.3) character columns when this bit is set to a zero. the internal (pseudo-xgmii) error character can be set to a value other than 1fe?h by writi ng the value (without the k bit) to register 3.c002?h or 4.c002?h. similarly, the internal (pseudo-xgmii) idle character may be changed using registers 3.c003?h and/or 4.c003?h. the pseudo-random xaui/cx4/lx4 idle /a/k/r/ generator can be disabled by clearing the akr_sm_en bit in register 3.c001?h (pcs) or 4.c001?h (phy xs). to disallow complete regeneration of the inter packet gap (ipg), it would be desirable to clear the trans_en bit in register 3.c001?h/4.c001?h. recommended analog power and ground plane splits the bbt3821 high-speed analog circuits as well as high- speed i/o draw power from the analog power (v dda ) and (shared) ground gnda pins/balls (pins or balls will be used inter-changeably through out this document). in order for the bbt3821 to achieve best performance, the v dda and gnda should be kept as ?quiet? as possible. there are also data stop data start scl sda t sclh_l t scl_dav t sda_clv t sda_clv bbt3821
71 two further analog supplies, v ddac and v ddav for the cmu and vco respectively. these two also need to be kept quiet. the v dda, v ddac, v ddav and v dd voltage requirements of the standard bbt3821 are all 1.5v (for the low power lx4-only version 1.355v). the ripple noise on the v dda# voltage rails should be as low as possible for best jitter performance. therefore, in the layout, each v dda should be decoupled from the main 1.5v(1 .4v) supply by means of cut outs in the power plane, and the power to the individual v dda areas supplied through ferrite beads (1a capability is recommended). the cut out spacing should be at least 20mil (0.5mm). a ?quiet? analog ground also enhances the jitter performance of the bbt3821 as well. a similar cut out in the ground plane is recommended, to isolate the analog sections from the digital ones. recommended power supply decoupling for the bbt3821, the decoupling for v dda v dd, v ddac , and v ddav must all be handled individually. v dda (1.5v/1.355v) provides power to most of the analog circuits as well as the high speed i/os. the analog power supply v dda must have an impedance of less than 0.4 ? from around 50khz to over 1g hz. this can be achieved by using one 22f (1210 case size, ceramic), and eleven 0.1f (0402 case size, ceramic), and eleven 0.01f (0402 case size, ceramic) capacitors in parallel. the 0.01f and 0.1f 0402 case size capacitors must be placed right next to the v dda balls as close as possible. note that the 22f capacitor must be ceramic for the lowest esr possible, and must be of 1210 case size or better to achieve this. the 0.01f capacitors should be of case size 0402 or better, offering the lowest esl to achieve low impedance towards the ghz range. also, note that the ground of these capacitors must be well connected to gnda. similarly v ddac and v ddav (also 1.5v/1.355v) supply the frequency (and hence jitter) determining sections of the bbt3821. they should each be decoupled using one 22f ceramic lowest-esr-possible capacitor, and one each of 0.01f and 0.1f. the latter especially should be close to the respective balls of the device, with a low impedance trace-path to the device and to gnda. the v dd (1.5v/1.355v) supply is the power rail for the bbt3821core logic circuit. for this supply, at least three 0.1f (0402 case size), three 0.01f (0402 case size) and a 10f (tantalum or ceramic) capacitor are recommended. place the 0.01f and 0.1f capacitors as close to the v dd balls as possible. v ddpr (recommended 2.5v or less) is used for certain esd protection circuits; at least two 0.01f (0402 case size), and two 0.1f (0402 case size) capacitors are recommended. place the 0.01f and 0.1f capacitors as close to the v ddpr balls as possible. if the v ddpr supply can be applied faster or earlier than the v dd supply, it is recommended that a limiting clamp be provided to maintain the absolute maximum rating limits of table 102. a simple example of such a clamp is given in figure 25, using a small shunt regulator. since the power dissipation of the regulator is negligible except during the supply power-up time difference, no special heat dissipation precautions are needed. xenpak/xpak/x2 interfacing the bbt3821 incorporates a number of features that facilitate interface to the (pin-function-compatible) xenpak, xpak and x2 interfaces. the relevant 3.125gbps serial lines in the BBT3821-JH are brought out in exactly the correct order to be connected to the edge connector, minimizing any layout problems, and the use of vias, in pcb design. furthermore, the bbt3821 device also incorporates the logic required to handle the tx_on/off and lasi pins, to interface (via an i 2 c bus) with an eeprom (or similar device) to load the nvr space with all the mdio register values specified in the xenpak msa r3.0 specification (which are referenced, with only minor oui-number type changes in the xpak and x2 spec ifications), and to transfer digital optical monitoring (d om) information from typical i 2 c-interface devices into the xenpak (etc.) specified mdio space. if the xp_ena pin is high at the end of hardware or full mdio reset, the i 2 c engine will attempt to read whatever device is on the bus at the a0:0 0?h address. if it succeeds, it will read the a0:01?h address, and so on, till it reaches a0:ff?h. if at any point the number of i 2 c acknowledge (ack) failures on any address exceeds the limit set in register 1.8005?h (see table 20) the nvr load will fail, and the result of the operation in 1.8000?h will report the failure. if a suitable device with 256 bytes at the a0 device address (either a serial eeprom device like the atmel at24c02a or a device such as the micrel mic3000 or the dallas semiconductor ds1852) is present, the data in it will thus be transferred to the mdio register space. most of this data is merely copied to the mdio space, but a few specific items (listed in table 22) have additional effects, for example providing the ?package oui values for 1.14:15, or the dom capability bits in the 1.807a register. if these dom capability bits (lis ted in table 23) indicate that the 2-wire bus has a device ( again such as the micrel mic3000 or the dallas semiconductor ds1852) oriented to performing the sff-8472-defined dom function, the bbt3821 will attempt to read the data from that device into the mdio dom alarm and warning thresholds registers (see table 32), and the current a/d value and flag registers (see table 33, table 36 and table 37). if the xenpak dom operation control and status re gister (see table 38) is set appropriately, the dom current a/d value and flag registers will be updated periodically from all the dom device(s), via the dom device pointers in table 54 and table 55. see "i2c interfacing" below for more details. bbt3821
72 cx4 interfacing the relevant 3.125gbps serial lines in the BBT3821-JH are brought out in exactly the correct order to be connected to the cx4 connector, using either the top layer of the pcb for striplines, or an inner layer for microstrip lines, without any necessity for crossing the various leads. there are gnda pins between each serial line pair, and special care has been taken to facilitate the optimal separation of the tx3 and rx3 line pairs. increasing the pcb trace separation between these pairs, and adding a stri p of gnda, will decrease the crosstalk effects, which are no rmally most severe for this pair. note that the cx4 output will not reliably meet the cx4 specification with the v dda v dd, v ddac , and v ddav supplies as low as 1.344v (1.4v-4%), so the low power version device is not recommended for this usage. lx4 interfacing in lx4 mode, the serial pma/pmd outputs are by default set up without pre-emphasis, since it is anticipated that the laser driver circuits will be located only a short distance away. this can be overridden by the auto-configure capability, if desired, to accommodate a lossy or long interconnect, and to provide enhanced high-frequency drive if needed by the laser driver. similarly, the receiver inputs are set up by default without equalization. agai n, this can be overridden by the auto-configure capability, if desired, to accommodate a lossy or long interconnect, and to compensate for poor high- frequency performance in the photodetectors. under ?standard? part conditions, these signals are xaui- compatible. under the ?low power? supply voltage conditions, the output drive may fall below the xaui specification. this is normally not a problem for laser drivers, but if low power operation is desired, this should be checked. many lasers and laser drivers require setting of the laser bias and modulation currents, to optimize the performance. this is frequently done via digitally controlled resistors or current sources, many of which have i 2 c interfaces for setting the values, often as a function of temperature. by ensuring that the device addresses of these circuits are distinct from those of the nvr, and any separate dom circuits provided, the i 2 c interface of the bbt3821 can be used to initialize the setups of these circuits. the technique described under ? byte writes to eeprom space ? on page 19 can always be used in this case. this can be done after a module is fully assemb led, if necessary using one of the ?spare? pins on the xenpak connector, or a gpio pin, to enable writing to the relevant circuits. mdio/mdc interfacing the mdio and mdc lines in the bbt3821 have been designed to maximize compatibility both with older systems, that may use logic levels compatible with 3.3v cmos designs (such as specified in ieee 802.3- 2002 clause 22), and newer systems compatible wit h the levels specified in the 10ge specificat ion ieee 802.3ae-2002 (based on 1.2v supplies), and systems using intermediate supply voltages. in general, no problems should occur in any such applications, provided the resistive pull-ups go to no higher than a nominal 2.6v. however, the bbt3821 is inherently a very high-speed device, and the falling-edge-rates generated by the part can be qui te high. to avoid problems with excessive coupling between the mdio line and the mdc line, and consequent gener ation of false clock-edges on the mdc line, and hence in correct mdio operation, the mdc line has been given a schmitt trigger input. note that the mdio registers wi ll not be written till after up to three additional clocks after the end of a write frame (see figure 15). it is recommended that mdc run continuously, but if this is not possible, extra clocks should be added after a write. these will count toward the preamble for the next frame (except when the byte written caused a soft reset, see figure 17, and extra preambles may be required). i 2 c interfacing the i 2 c interface, normally used to provide the nvr requirements for xenpak/xpak /x2 msa modules, consists of two lines, scl and sda. these conform to the i 2 c specification (?the i 2 c-bus specification, version 2.1?, at url http://www.semiconductors.philip s.com/acrobat/literature/93 98/39340011.pdf ) for standard-mode (to 100khz) and fast- mode (to 400khz) operation. the bbt3821 is a bus master, and expects to see the nvr ee prom and/or dom circuits as slaves. particularly if fast-mode operation is desired, the capacitance of and coupling between the scl and sda lines should be minimized. since thes e lines are ?open drain?, the rise time of the scl line will inherently stretch the ?low? time of the line, as seen by the bbt38 21, due to the effect of the rc time constant of the pull-up resistor and the line capacitance. this will slow down the operation of the interface. if the other i 2 c devices on this bus are 3.3v devices, their v ih levels should be checked to ensure satisfactory logic operation if the pull-up resistors are taken to a nominal 2.5v. if they will work from a lower voltage, the resistors can be taken to any such voltage down to the vdd level. the above reference incl udes charts for the values of the resistors, based on the capa citance of the line, and the desired clock rate. for the default operation speed of nominally 100khz, a value of 5k ? to 15k ? will normally be suitable, while for fast-mode operation, 2k ? to 4k ? will normally be needed. if a 2.5v supply is not available, resistive dividers may be used to ensure that the signals on the bbt3821 lines do not exceed that level. some examples are shown in figure . dom interfacing the nvr interface has already been discussed above (?xenpak/xpak/x2 interfacing? on page 71). the bbt3821 also includes a flexible dom interface. see ?dom registers? on page 16 for details. most laser drivers and receivers bbt3821
73 (tosa and rosa) include monitor outputs reflecting the laser bias current, the laser output power, and/or received optical power. some of these analog outputs are referenced to gnd, others to an appropriate v dd. for use in the optional dom system, these values need to be converted to digital values, compared with alarm and warning levels, and made available as both digital values and as flag registers and alarm signals. since the wdm 4-lane dom interf ace ideally needs to find ?furthest-out-of-range? values, it will operate most effectively using a single dom control and conversion device. suitable parts include the cygnal c8051f311 device, which can handle the 12 monitored values, 4 v dd signal reference levels, the scl and sda signals, and the lasi-driving tx_fault, opttemp, optxlbc, optxlop, and oprxop signals. the device includes a 10-bit differential adc, a temperature sensor, an onboard clock oscillator, and an i 2 c bus controller (called the smbus system by cygnal), which should be set up as a slave. the nvr information can all be stored in the on- board flash eeprom memory, making for a single nvr/dom/lasi device. if additional i/o signals are required, the similar c8051f310 has them available, for an increase in board area. alternatively, an analog multiplexer such as the maxim max4694 could be used to switch inputs between different lanes, under i/o pin control. a similar series of pa rts are available from cyex as the slc series. these parts also include dacs for laser control functions. if this type of device is used, the bbt3821 should be set up in ?direct dom? mode (see table 51 and "dom registers"), and it will then be able to download the complete dom bl ock as required. an alternative is to use a device specifically designed as a dom device, such as the micrel mic3000 or the maxim/dallas semiconductor ds1852. each of these is a single lane device, and is oriented to fulfilling the requirements for sfp modules and the sff-8472 specification. although very si milar, the latter has some small differences from the xenpak dom specification, which can cause problems. if a single device is used, it can be configured as a single dom device, typically at device address a2, and used to monitor, for example, the average (sum) of the desired values. the thresholds, monitored values, and alarm and warning flags will conform to the required behavior for single-lane monitoring (see note 2 to table 27 in section 11.2.6 of the xenpak r3.0 specification). if the bbt3821 is set up in ?direct dom? mode (see table 51 and "dom registers"), the single-lane values will be transferred to the md io register space. such an arrangement may be very suitable for use in a cx4 module, where it could be desirable to measure the temperature, although the ?laser bias current?, ?received optical power?, etc. have no meaning (and ?digital optical monitoring? is a misnomer!). note that the ds1852 does not provide a sufficient nvr block for xenpak, and an additional 256-byte eeprom su ch as an atmel at24c02a will be needed. using four of the single-lane devices mentioned previously, the system can monito r all four lanes. a first download of a single device would load the fu ll 256-byte space, and the bbt3821 should then be set in ?indirect mode? (see table 51 and "dom registers"), with the pointers appropriately reset. for the mic3000, three of the four devices should have their ?i 2 cadr? values changed (e.g. to b2, c2 & d2), leaving the fourth at the default dom address a2. the nvr space will be provided by the a0 space in that last device, while the dom spaces for each of the f our lanes are accessed via the indirect device address pointers in 1.c01b:c?h, which would be set to a2, b2, c2 & d2 in the above scenario. the memory address values in 1.c019:a?h would be left at the default 60?h value. to util ize the ds1852, an eeprom is needed for the nvr at the a0 address space, and one lane?s ds1852 should have the d0h device address value at the a2 default value, and its asel pin sh ould be high. the others (also with asel high) shou ld have the d0h values set to an array of different device address values, for instance b2, c2 & d2 (as in the previous example), or a4, a6 & a8, and the same values also set in 1.c01b:c?h. a first pass will read the eeprom space in a2 .00:5f?h from the ds1852 device at a2, followed by the a/d and flag values from a2.60:75?h, and various other values to a2.7f?h. the space from a2.80:ff?h depends on the ds1852 table select byte (7f?h); if this is 0, the source data is empty; if it is set for table 03, the actual alarm and warning threshold values will be returned; if 01 or 02, the various eeprom banks, depending on the access level set. see the ds1852 data sheet for details. subsequent dom reads performed with indirect access can load the standard xenpak 4-lane a/d space from the four dom devices. open drain outputs from the dom devices can be pulled up via resistors to v dd , or any voltage between that and a nominal 2.5v. if a 2.5v supply is not available, resistive dividers may be used to ensure that the signals on the bbt3821 lines do not exceed that level. active pullup devices should have their outputs divided before reaching the bbt3821 pins. some examples of each are shown in figure . lasi interface the bbt3821 incorporates all the logic needed to control and enable the full xenpak/x2/xpak link alarm status interrupt (lasi) system, with several optional incorporated enhancements. many of the (s pecified and optional extra) inputs are derived from the status registers in the bbt3821 (see ?lasi registers & i/o ? on page 17, and figure 5), and the others are derived from a se t of input pins (see table 99) that would normally be driven by the corresponding status outputs of the either the tosa and rosa devices, or (if implemented) the dom devices. th e active polarity of these pins can be controlled via th e bbt3821 registers. since bbt3821
74 many tosa, rosa and lane-oriented dom devices have open-drain outputs that go high on an alarm condition, wire- and-ing these together for a four-lane indication is not possible (any ?working? lane masks the ?alarmed? lane(s)), some external gating may be re quired (typically a 4-input or or nor gate per alarm). note that the default polarity of these alarm inputs (active high) will be set after power-up, reset or a hard (d.0.15) softwa re reset, until the device is reconfigured. if a ho st-driven configuratio n is being used, the polarities (controlled by 1.c01d, table 55) should be set before the lasi enables (1.9 002, table 27). if the auto- configure system is used (see ?auto-configuring control registers? on page 16 and table 92), the configuration may take typically about 100 msec (see figure 18 and table 117), and there will normally be a brief interval during which the lasi interrupt is likely to be (i ncorrectly) activated. lasi host operations would probably normally ignore such ?glitches?, since the byte synch and lane alignment will initially be in ?fault? condition after such a reset (per the ieee 802.3ae specification), and so the relevant latched local fault indications will need to be cleared before lasi is meaningful, but it could be advisable to ensure that the additional indications are ignored or cleared in the same way before the full lasi system is activated. r1 68 d1 zhcs400 a b p3v3 vddpr u1 lmv431 2 1 3 reference vdd r2 10k from msa conn to bbt3821, pull-up resistors r3 12k figure 25. v ddpr clamp circuit cathode anode cathode anode rpu 12k tx_fault_3p3 ---each- - - 18k for mi c3000 tx_fault rpu 12k ---etc.-- - sda, scl tx_ena3p3_# rpu 12k rpu 12k raw_3v3 tx_fault_3p3 tx_ena# rpu 12k sda, scl raw_3v3 rpd 10k oprxop oprxop_3p3 from bbt3821 rpd 30k rpd 10k rpd 16k oprxop rpd 10k raw_3v3 ---etc.-- - ---etc.-- - tx_fault rpd 10k oprxop_3p3 rpu 12k ---etc.--- t o / f r o m 3 . 3 v e e p r o m f r o m / t o b b t 3 8 2 1 t o 3 . 3 v t o s a f r o m 3 . 3 v o s a ( o p e n d r a i n o n l y ) f r o m 3 . 3 v o s a ( a c t i v e p u l l u p ) figure 26. resistive divider circuits bbt3821
75 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com intersil corporatio n contact information technical information can be found via the web page at http://www.intersil.com/design/ contact intersil technical support by phone at 1-888-intersil or 1-888-468-3774. ordering information product frequency package order part number bbt3821 2.488gbps- 3.1875gbps 192 ld ebga-b package; 17x17mm BBT3821-JH bbt3821 low power 2.488gbps- 3.1875gbps bbt3821lp-jh bbt3821

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